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ADS54J54EVM: Question about JESD204B data lanes length match

Ramin Fardi
Intellectual 270 points
Part Number: ADS54J54EVM

Hi,

In the schematics of  ADS54J54EVM  page 4 it ca be read: 

"HIGH SPEED DIFF PAIRS
DA*, DB*, DC* & DD*
DO NOT HAVE TO MATCH EACH OTHER IN LENGTH
THE P & N ON EACH PAIR MUST MATCH IN LENGTH"

But when I look at the PCB tracks for these signal they are in fact matched in length with each other as can be seen below. I am doing a board with exactly the same configuration that is trying to connect to a FPGA through FMC connector, how should I do?

Regards/Ramin

  • 0
    TI__Guru* 91947 points

    Ramin,

    We have a habit of routing lanes the same length as this was the norm for LVDS signals. When using JESD though, the elastic buffer allows for far less trace length matching. You should still keep the P/N signals matched, but as far as the data lanes are concerned, you could have several inches of length mismatch. The trace prorogation mismatch will be absorbed by the elastic buffer.

    Regards,

    Jim