This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

ADS131A04: DONE/CS pin in Synchronous Master SPI Mode

Part Number: ADS131A04

Hello,

Is it absolutely necessary to connect DONE to CS in Synchronous Master SPI Mode?

In the EVM user guide, it looks like CS is left floating in Master mode:

If CS can be left floating (or should it be grounded?), what should be done with DONE?

Thanks,

Michael

  • Michael,

    If there is only a single device, the DONE pin should be connected to the /CS pin. I believe that the reason it is grayed out is because the synchronous master mode can be used with multiple devices in a daisy chain. In that case you would tie the last DONE pin of the chain back to the synchronous master.

    I believe the synchronous master still needs the /CS connection for operation, so it shouldn't be left floating or grounded.

    Joseph Wu

  • Michael,

    Also, I noticed that you called. If you need a quick confirmation, I'm at my desk now and you can call back.

    Joseph Wu

  • Michael,

    I'll check with the designer on the master mode note in the EVM circuit. In the mean time, this post has a list of some of the errors I've noted in the EVM circuit:

    ADS131A04EVM: D3 RED LED - Data converters forum - Data converters - TI E2E support forums

    e2e.ti.com
    Part Number: ADS131A04EVM Hi, As I plug in the EVM to my host computer, the D3 LED glows. The EVM stays in the D3 LED on state for a variable time. Sometimes

    Joseph Wu

  • Michael,

    I've talked it over with the designer and the DONE should be connected to /CS.

    In synchronous master mode, the /DRDY acts as the /CS for the slave processor. However, the /DRDY indications are all controlled by changes in the DONE pin. Because of this, the DONE pin needs to be connected to the /CS. It looks like the EVM misses this connection, even with the settings of S7.

    Joseph Wu

  • Joe,

    So does the EVM just not work in master mode?

    Michael

  • Michael,

    Correct. I believe that the EVM is designed for only asynchronous interrupt mode.

    Joseph Wu

  • Thanks Joe. My only ask at this point would be an update to the User Guide to make this clear. I'm not sure why it references master mode multiple times if it's not even an option.

    Best,

    Michael

  • Hi Joe,

    The timing diagram for master mode does not include CS or DONE, and it is stated that "After the LSB is shifted out DRDY returns high, completing the data frame". Is it just assumed that CS and DONE are already connected and therefore the last LSB causes DONE to flip which flips CS which then flips DRDY?

  • Michael,


    Just to follow up after our call, the /DRDY is driven by the SCLK to complete the data frame. However it is driven by the /DONE connection to /CS to start the data frame.

    Again, I'd agree that the EVM isn't clear on the option of using the synchronous master mode. There isn't a connection for the M0 to M2 selection to the microcontroller to identify the mode of operation. I believe the software is designed for asynchronous interrupt mode alone. The note for synchronous master mode is for using a separate microcontroller to drive the connections on J3.

    Let me know if this covers your customer's question. I'd be up for another call if necessary.


    Joseph Wu

  • Joe,

    Thanks a lot for your help, I think this should be good for now.

    Michael