Other Parts Discussed in Thread: DAC5672
The DAC5672 operates in Single-Bus Interleaved mode.
Mode = 0, sleep = 0.
RESETIQ=0，SELECTIQ = 1，
Clkiq and wrtiq are the same 50Mhz continuous clock. DA is a 10Mhz period change data (continuous addition, then loop)，changed when Clkiq and wrtiq Negative edge。 However, the output does not change, it output 400mv and 600mv for the A channel, and 900mv and 100mv for the B channel. There is no change after the fpga program is programed. Should it be a 10Mhz cycle change output? What can cause this problem. Thanks
