• State TI Thinks Resolved
  • Locked Locked
  • Replies 1 reply
  • Answers 1 answer
  • Subscribers 46 subscribers
  • Views 239 views
  • Users 0 members are here
Support feedback
Options
Options
Similar topics

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

DDC264EVM: DDC264EVM

Noushin Ghaderi
Prodigy 50 points
Part Number: DDC264EVM
Hi, 
I have bought a DDC264EVM board for providing a regular data capturing . However, using its interface, we can just capture the data when we push a button.
So I am trying to make my own interface for this DDC264EVM board.
I am using Labview to create this interface.
I could provide all the subvi s using the USB-IO-VB6.dll file.
My question is about the programming FPGA register using WriteFPGARegsC() function.
Actually I am completely confused how I can quantify the parameters of this register ( I mean DUTSelect, Array_Regsln, Array_RegsOut, Array_RegEnable)
for example how I can determine the ConV signal parameter or clock frequency or DVALIDS parameter, using these function?
There are some explanation in user guide of USB_IO_VB6.dll in the table with the title of "the register of FPGA to be configured"
But I still cannot figure out how to quantify this register.
Would you please explain me, what should I put in the arrays variable of this function for proper working?
Thank you for your assistance. I really appreciate it.
  • 0
    TI__Mastermind 49666 points

    Hi Noushin,

    The default MCLK frequency is 80MHz.

    CLK frequency, DCLK frequency, and CLK_CFG frequency are derived from the respective count values referenced to MCLK (80MHz).

    For example, the default count value programmed to CLK_HIGH and CLK_LOW is 7. Total count value is 2*(7+1) = 16. CLK frequency will be 80MHz / 16 = 5MHz.

    Similarly, DCLK_HIGH and DCLK_LOW counts are 1. Total count value is 2*(1+1) = 4. DCLK frequency will be 80MHz / 4 = 20MHz.

    In a similar way, you should be able to derive the CLK_CFG.

    CONV is based out of # CLK counts. In the GUI, the default count value is 1600. That corresponds to 1600/5MHz = 320us.

    To begin with, you can program the EVM GUI default values and read back the values and then adjust the values based on your application requirements.