ADS1241: reg write and read issue

Hi user6216951,

Welcome to the E2E forum!  Thanks for sharing the logic analyzer data.  Can you also send me your schematic?  Make sure that you don't have any floating digital input pins.  In particular, make sure that POL is pulled high and not floating.  What crystal  or clock frequency are you using for the master clock?  Have you verified that the clock frequency is as expected?

Also, is this a prototyping solution?  Make sure that you have a good ground, and that there is no glitching on the signal lines.  You should also try to monitor as close to the ADS1241 as possible.

Is the issue only on some register writes/reads?  Do you see any consistency as to a particular register?

Best regards,

Bob B

Hi Bob,

    POL is pulled high, we verified on the temporary prototype that the crystal oscillator is close to the ADS1241 and the operating frequency is as expected. The same register is written and read to the expected number of times, sometimes it can be successful, sometimes it needs to be repeated several times to succeed.

Hi user6216951,

Thanks for the information.  A couple of additional pieces of information would be helpful.  Is this a prototyping situation, or is the system on a PCB?  Is your micro running at 5V?  Where are you placing the Saleae probes (are they closer to the ADS1241 or closer to the micro)?

If you have a Saleae with an analog capture, I would suggest using it to verify if there is noise or delays in the edges (or you could use an oscilloscope).  The logic analyzer may be set to slightly different thresholds than the ADS1241 inputs for Vil and Vih.

You could try slowing down the SCLK to see if that makes any difference.  If you are driving the ADS1241 inputs with 3.3V logic from a 3.3V micro you will also see an issue as 3.3V logic is not going to give consistent results as the Vih at 5V DVDD is 4V.  If you have level shifting there could be delays affecting the edges of the data relative to the clock on data coming from the ADS1241.

Best regards,

Bob B 

Hi Bob,

   It was originally built on a temporary circuit. The Saleae probe was placed close to the ADS1241. The following schematic is now running on the PCB. The phenomenon is the same as before, but after writing to the register, it runs like IOCON=0x13, DIR=0x03. After D0, D1 can output high level.

  When ignoring the write and reading the register value is not expected, we will Vref=2.5V, the signal to be measured on the AIN5 pin is 0~5V, AIN6 is the 2.5V reference voltage, used to measure -2.5V~+2.5 When the application scenario of V,

The source initialization steps are as follows:

ba_ads_writeReg(ADS1241_SETUP, 0x00) ; //PGA=1

ba_ads_writeReg(ADS1241_MUX, 0x56); //AIN5+, AIN6-

ba_ads_writeReg(ADS1241_ACR, 0x00); //Bipolar, RANGE=±VREF, DR=00(30Hz)

ba_ads_writeCmd(ADS1241_SELFCAL); //Offset and gain calibration

. . . . Waiting for 6 DRDY cycles

Read OCR=0x000101, FSR=0F0701

......

After the DRDY is ready, call the RDATA command to read the AD sample value.

When AIN5=3.111V, the AD value is 0x1FD81F. When it is slightly larger, the AD sample value becomes from 0x000000.

What is the cause of this phenomenon?

Hi user6216951,

One thing that is still not clear.  Is the micro you are using also powered by 5V?  I also find it interesting that the data example you showed starts with byte 1F and ends with byte 1F.  Do you have updated Saleae plots of the communication that you can share?

When sending commands, there must be sufficient time for the command to be decoded and a proper response loaded  before attempting to read.  See the timing diagram on page 6 of the ADS1241 datasheet.  In particular notice the t6 timing.  You must make sure that you have allowed sufficient delay between the RDATA, RDATAC, RREG and WREG commands before the next set of SCLKs are set in the transmission sequence.

Best regards,

Bob B

Hi Bob，

    MCU powered by 3.3V，MCU and ADS1241 communicate through high speed optocoupler(PC457L 1Mb/s) isolation，By continuing to increase the AIN5 voltage slightly, when the read AD value is greater than 0x1FFFFF, it starts to change to 0.

  In addition, after sending the command, the delay t6 reached 16.9us, which has reached the requirement of not less than 50 tOSC Periods.

Hi user6216951,

There appears to be some possible SCLK glitches based on what I see with the middle byte of the RREG of the DOR registers.  I would highly recommend observing the communication using an oscilloscope and observe the rising/falling edges of SCLK to see if there is a spurious SCLK or perhaps a non-uniform clock where there is significant differences in the duty cycle for high and low time.

Best regards,

Bob B 

Hi Bob,

    We used an oscilloscope to capture the waveform of the IOCON register command captured on the SCLK and Din pins near the ADS1241.

    The following figure is a partial enlarged view of the starting part

Hi Bob,

    From the phenomenon we encountered, write IOCON = 0x13 by WREG, configure AIN0, AIN1, AIN4 as data insertion, and then write the corresponding substitution of DIO value to get the correct output. The write communication of ADS1241 is normal, but when using RREG and RDATA commands to read data from ADS1241, I did not get the correct expectation. In response to this phenomenon, I have replaced 3 ADS1241 chips. Adjusted to 0 for repeated verification, and at the same time, repeatedly checked the following figure in the data sheet:

The following figure is the ADS1241 crystal frequency: 4.9152MHz, POL = 0. After sending the reset command, wait 14.6ms, and then use the RREG command to read the waveform of the SETUP register.

According to the above figure, you can compare the data sheet:

Hi user6216951,

I apologize for the delayed response due to an extended holiday weekend in the USA.  If you set POL to 0 or to 1, you should see similar results as the data will change on the first edge of SCLK and should hold steady on the second edge of SCLK.

There will be some differences with respect to going through isolation.  When writing to the ADS1241 both the SCLK and MOSI will be delayed by the same amount.  However, when reading results or register data, the command will be clocked with the same phase as SCLK, but the reading of data will be delayed by an additional delay through the isolation when returning to the micro.  The micro sending the SCLK will not consider any delay at all and can potentially clock in the data prematurely.  So the ADS1241 will have the SCLK and MOSI delayed by the isolation, and the micro will have an additional delay of MISO because of the isolation on the return path.

In the latest Saleae plot there is what appears to be a spurious SCLK. Notice the data transmitted from the ADS1241.  The MISO transitions on the rising edge except for the last MISO going high.  This occurs slightly after the 6th SCLK of the byte being transmitted.  Notice that the earlier transitions are taking place on the rising edge, but this last transition does not.  Something is interfering here.  I have mentioned this previously in response to your post from 11/25/2019.  You need to consider both the transmission delays, and any spurious SCLKs on the signal paths.  This could be due to wiring issues or poor grounding.

Best regards,

Bob B