DAC39J84: DAC39J84 4421 configuration issues

Hi again, for some reason the image with the configuration setup didn't load properly. Here it is. Another thing I forgot to mention but I think it's obvious, is that the DACCLK and the SYSREF are present from the very beginning.

Hi Jim,

Thanks for the fast reply!

I'm using the PLL as an easy way to check that I get a clock to the device, but yes it can be disabled. The DACPLL is locked (bit 0 at register 0x6C is 0).

About the unused lanes. Should I keep them like that (sending comma chars indefinitely)?

I'll check out your configuration to see if that works for us.

Thanks

Javier,

You can keep send comma chars on unused lanes. The DAC will ignore these. An easier way to verify if the DAC is getting a valid clock is to operate the part in NCO only mode. 

Regards,

Jim

1325.DAC38RF82_NCO_CW.pptx

Hi Jim,

It seems the configuration you sent me worked and we can see signals at the output.

This is a bit off the topic but we see that the DAC introcudes overshoot/undershoot whenever tha sample is updated/changed so the signal looks quite bad. It can be easily filtered out but I believe the DAC should behave. The board uses the output circuit depicted at the DAC39j84 datasheet (page 77) with a TC1-1-13M+ balun from Mini-Circuits.

I suspect of an impedance missmatch of some kind causing this effect, but I could use some advice from you.

Kind regards

Javier,

Is there a chance the data samples are out of order coming out of the FPGA? See attached file of what I think is your data sent to the DAC with my setup.

Regards,

Jim

Hi Jim,

Could you elaborate a bit more about this? Maybe I'm missing something here...

Data is fed from an FPGA based 16b NCO (IP generated). We byte swap the samples since for 442 MSB is sent first. I don't see a way that data is out of order (in 442 mode each lane feeds a DAC). On top of that we have seen the same behaviour on 841 mode.

Thanks

Javier,

Each lane is sending data to a converter. If the samples came out as 2,1,4,3,6,5,.... instead of 1,2,3,4,5,6,... you would see what you are observing I think.

Regards,

Jim

Hi Jim,

I've analyzed the samples with signal tap, moved them to excel, plot them and they show a nice and clean sinewave.

On the other hand, if you look at the first picture I sent you, the perturbance is exactly at Fs. If the samples were not ordered as you suggest, then the perturbance would be, at least, at twice the sampling frequency.

You can count the peaks within a horizontal division, they are exectly 5 max and 5 min, with 5 samples every horizontal division (10 ns) running at 500MSps.

Cheers

Javier,

I am assuming this is a custom board. Can you send us your schematics? Can you also explain the last two scope screen shots you sent. Not sure what the second screen shot was showing.

Can you try generating a tone that is the same frequency as the one from the FPGA data using the DAC internal NCO only and see how this output compares to the FPGA data? This should tell us if it is a board issue or not.

Regards,

Jim

Hi Jim,

Yes, this is a custom board. It's a FMC231 from Vadatech (AC coupled outputs). Unfortunately I got no schematics, just a very simple block diagram with the clocking network. The images I've sent are as follows:

The first image is a 20MHz sinewave from the FPGA using a IP-based NCO. The scope shows two DAC channels working on 442 mode with 500MSps (x2 interpolation).

The second image is the same but one of the outputs (yellow) has been filtered with an external RF low pass filter. This image also shows an FFT plot but I don't think it's relevant. The FFT shows a 20MHz peak with two tones at 500+/-20 MHz. I personally think that's an artifact and not a real mixing.

I'll try the NCO only mode. Can the DAC39J84 work without an incoming signal? I've look at the datasheet and it's only suppossed to mix the NCO, so I'll be driving a constant value at the DAC, so the NCO is mixed with something different than 0. Otherwise please let me know.

Cheers and thanks for your help!

Hi Jim,

We tested the NCO only mode (NCO in fine tune and SIFDAC value) and still shows the same behavior...

Cheers

Javier,

Attached are plots with our EVM using both the NCO and the FPGA to generate the 20MHz output. If you are not seeing this, I think there is an issue with the DAC output circuit you are using.

You need to make sure the voltage on the IOUTP/N pins do not exceed the max compliance voltage of 0.6V and that the full scale output current does not exceed 30mA or you will see increased signal distortion. What value are you using for the Rbias resistor? This is connected between pin G10 and GND.

Regards,

Jim

20MHz NCO and FPGA Outputs.pptx

Hi Jim,

I'm still surprised there is some distortion on your output. Not as bad as mine though. I used to work with the same chipset on the Abaco Systems FMC144 and FMC120 and I don't remember having these issues.

We've risen a support ticket to the board manufacturer to see if we can figure out what is wrong.

Thanks a lot for your constant and fast support. Pretty much appreciated!

Kind regards