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DDC264EVM: DDC264EVM Noise on channels

Part Number: DDC264EVM
Other Parts Discussed in Thread: DDC264

Hi.

I'm using DDC264EVM and I have some problems. 

1.when I'm using Vin to connect a SiPD, I change the light of room or make it dark, but by clicking on fast data key in software, I get the plot  changing very slow. for example from full scale, when I put it immediately in dark space, it receive to 0-5 % of full scale, but in a time about 10-20 seconds. every time I click fast data see the plot just changed about 5%. Although My SiPD have 20 MHz Freq. How can I see Immediate changes? 

2. When I'm using Vin to connect a detector, and just connected one of jumpers on the Analog interface board containing resistors, for example,J10. when I get fast data on default settings in software, I see for example a 50 % of full scale on some channels that connected to the 1-2 input of J10 and other channels are not connected anywhere have a value near zero. but when we check other channels more, looking there is about 0-1 % of full scale on them as noise. it if we divide it to 100 it shows only 7/20 of bits are working accurate but not other 13 LSB bits?  any other faced this problem? is my Evaluation board working good?

this is channels I see 80 % of FS:

and this is the noise on other channels zoomesd:

3. In test mode we disconnect Analog Interface Board and click fast data and see there where about 0.01 % noise that show there is about 13 bits have accurate value but 7 others not? is it normal? 7 bits noise in test mode? and why it has negative value?

this is what I see:

4. in ddc264 datasheet wrote max frequency for DCLK is 32 MHz but in the software the default value is 40 MHz?

5. I use this devise in free run mode, but when I see the CONV,DCLK & DOUT Pins on oscilloscope, CONV always works,but DOUT and DCLK just seen when I click fast data key? why this happens?

6. what do resistors series to vin do? is this for any safety reason or protection? I mean this resistors

Thanks

  • Can anyone help me with this problems?

  • Hi,

    Quickly...

    #1 I am not sure if you are talking about the delay between the time you press the button to the time you see the result on the screen. If that is the case, it probably has to do with the sampling time (# of samples x sample period) + the buffering/transmission/processing and display on the PC. The board was not intended to be used as a real time capture...

    #2 Can't really tell without exact numbers but looks to me fine. I mean, the channels that do not get any input will have around 4095 code (+offset). The zero input does not give zero code (this is by design, to give some room towards the negative side for system debugging reasons). Please see datasheet for input to output transfer characteristics. Nevertheless, if you are seeing noise of 1% of FSR on those channels, that is too much.You are probably picking it from some external interferer so may want to make sure the EVM is in a shielded box.

    #3 I believe that plot is showing you offset and noise. The center of each bar is the offset and the spread (height) of the bar is noise. Looks good to me. The number of bits flipping is not an indicator of noise (not directly). 

    #4 Yes, the DS applies but the EVM gives some margin for evaluation. As you may observe there is margin on the device usage but may not want to exceed the 32MHz specially when you start daisy-chaining devices...

    #5 This looks to me more like a scope usage, isn't it? But you are right on seeing the DVALID. If you don't press capture, the FPGA is giving CONV but is not reading the data out of the DDC. So, DVALID gets asses the first time but as no one reads it, it will get stuck low and only blip for very short time every time the conversion finishes, just to go back to zero (basically the opposite of normal operation). 

    #6 Replied here; https://e2e.ti.com/support/data-converters/f/73/p/864285/3202353#3202353

    Regards,

    Edu