ADC31JB68: ADC31JB68EVM Serial data output data

Hi Kiman,

What is the sampling rate that you are using? Have you also tried to use a ramp pattern?

Best Regards,

Dan

Hi Dan,

I am using 500 MHz CLK for the 500 MHz ADC sampling.

I also tested a ramp test pattern.

Thanks,

Kiman

Hi Kiman,

I am able to capture data with our data capture card (TSW14J56EVM) with the settings that you have shared. Have you configured the ADC31JB68EVM in accordance with the user's guided?

Can you please ensure that the JESD IP is configured to accept the 2 lanes of data as shown in the ADC31JB68 datasheet page 26?

Also note that the number of frames in a multiframe (K) defaults to 32.

Best Regards,

Dan

Hi Dan,

Here is my configuration for the Xilinx JESD PHY and JESD IP core.

Each lane has output data size is 32 bit and the total data size is 64 bit with GTH reference clock 250 MHz.

Figure 16 seems each lane data is 8-bit and 250 MHz update rate and make a 32bit for 500 MHz.

Default K I used 16 and need to change 32 as you recommended.

Can you please review my configuration, I have a no idea how to set up the LMFS 2111 from the Xilinx JESD IP core.

Hi Kiman,

I don't have much experience with initializing the JESD204B IP core, but most of what you have share looks "ok" to me (other than the K value). I'm also not sure about the LMFC buffer size (currently set to 1024, shown on the first image you shared). I'll have someone take a look to see if we can provide further help here.

I would also suggest reaching out to Xilinx to see if they can offer support on the FPGA side.

Best Regards,

Dan

Hi Dan,

Update: 

The Xilinx JESD 204 set Default K = 32, It happened Link error from ADC board and NO serial input from JESD IP.

Thanks,

Kiman

Hi Kiman,

I missed that the frame F is set to 2 in your JESD IP initialization, and it should be set to 1. I think this will correct the link error that you saw in your update.

Best Regards,

Dan

Hi Dan,

I changed the JESD204B setup as you recommended.

F=1, K=32

Serial-0 Data looks fine I can see clean sinewave.

But still Seral 1 is random data. 

The lane 1 serial 0, JESD output rate is 250 MHz 32bit, If I split two 16-bit data and intervening then it makes 500 MHz 16bit?

Hi Kiman,

I'm not certain I follow your last question. Do you know what data is missing? Since this is a one channel device, isn't the sinewave being faithfully captured? Are the top two rows, that have the sinewaves, representing both lanes?

Best Regards,

Dan