ADS1281: ADS1281 PCM encode spec

Hi Kailyn,

The M0 and M1 signals are serial bit streams that can be read directly at the output of the Delta-Sigma modulator, bypassing the built-in digital filter in case you wanted to implement your own digital filter (using a DSP or FPGA for example) with a different type of response.

Y[n] is an array of signed integers, representing the modulator's quantization level, where "n" represents the array index.

M0[n] and M1[n] are bit-streams (which can be represented as an array of 1's and 0's) and are combined according to equation 1 to calculate the quantization level. For example, the "6M0[n-3]" term is taking the the value of M0 from three samples ago and multiplying it by six. Note because of the "M0[n-4]" term, you have to collect at least four bits from both the bitstreams before you can calculate the integer value of "Y[n]".

Hi user6310626,

Please refer to this Excel file: ADS128x-Bitstream.xlsx

NOTES:

• To simply the conversion from the bit streams to voltages, I used "-1 in place of "0" values on M0 and M1. (NOTE: This is random data, since I didn't have a real dataset to use as an example).
  
  
• The M0 and M1 bits are summed together according to equation 1. Using "-1" in place of zeros, the integer values of Y can take on values between -49 and +49. (If you don't make this substitution, you'll get values between -24 and +25, which results in a small offset near mid-scale).
  
  
• The integer values for Y would then be passed into your digital filter and the output would need to be normalized to account for the filter gain. For this example, I just computed the average value of Y for the entire dataset...You should end up with a value between +/- 0.8.
  
  
• Next, I multiplied the average value of Y by a gain factor of 1.25 V/V since the modulator one's density only ranges from 10% to 90% (i.e. only 80% of the modulator output range is utilized) this compensates for the modulator's attenuation of the input signal.
  
  
• Finally, multiply that value by the full-scale voltage (+Vref / 2) and you have the average input voltage.

Alternatively, you don't have to use the ADS1281's modulator output mode to implement your own filter. To save on processing power you can instead configure the ADS1281 to use the SINC filter and run it at a faster data rate. After collecting the ADC data (filtered by the internal SINC filter) you can then pass this data to your post-processing filter in your FPGA to apply an additional filter. Using the ADS1281 this way, you benefit from not having to capture the modulator data at the higher mod clock frequency, and the built-in SINC filter provides some additional anti-aliasing for your post-processing filter.

I hope that helps!