ADS1260-Q1: Conversion latency vs data rate

Hi Ritesh U,

Conversion latency is defined as the time from the start of the first conversion, by taking the START pin high or sending the START command, to the time when the conversion data are ready. The order and the decimation ratio of the digital filter determine the amount of data averaged, and in turn, affect the latency of the conversion data.

ADS1260 ADC is a delta-sigma ADC with low latency digital filters. However even its latency is low, there is still a delay between the start of a conversion and the time when the /DRDY goes low. In the case of the 40 kSPS data rate on this ADC, the digital filter is a SINC5 filter which will take roughly 5 conversion periods to get the first conversion result. This is known as the conversion latency which is given for each data rate and filter type in table 8 in the datasheet.

Please notice this latency delay only applies to the fist conversion result and the rest consecutive conversion result will appear at regular intervals of the data rate. The FIR and sinc1 filter modes on this ADC are zero latency because the ADC provides the conversion result in one conversion cycle, which means you have to use either the SINC1 or FIR filter at one of their supported data dates if the conversion latency requires about 1 conversion period.

I hope this can help you understand.

Thanks&Regards,

Dale

Hi,

Thank you for reply.

As ADC has 4 channels which are multiplexed to single delta sigma core, so if I configure 1st channel and read data, 2nd channel and read data ...4th channel,

Will it add conversion latency in first scan of all channels and for 2nd scan on words i will get op at selected data rate?

What exactly 40KSPS specifies here? 

Hi Ritesh U,

The answer is yes when your ADC is configured to run in continuous-conversion mode. You can hold the START pin high or send a command (CONVRT bit in MODE 1 register) for continuous-conversion mode. Each time when you stop and start the conversion by toggling START pin or sending a command to the ADC, the internal digital filter will be reset and the conversion will be restarted, the delay is required and the latency will be observed.

Table 8 in the ADC datasheet shows the conversion latency for first conversion data by the order of digital filter and various data rate. I have included it as a screenshot below. For the subsequent conversion on the same channel, the output data rate is approximately equal to the data rate specified in the table. When you multiplex between input channels, the device assumes that the input on each channel is different and the digital filter must have settled data in order to provide fully-settled output data, so the latency specified in table 8 will be observed for first conversion on every channel.

When 40kSPS data rate is used (chop mode off,internal 10.24MHz clock), the conversion latency to first conversion is 0.179ms which is around 5586 SPS. Therefore, you can achieve 5586 SPS/4 = 1396.5 SPS data rate per channel when you multiplex all 4 input channels. If you take multiple samples on the same channel, the time for second and subsequent conversions will be 1/40kSPS = 25us.

Best regards,

Dale Li

Hi,

Ok, as I have to use all channels, continuous conversion on single channel will not be going to cover my design need, So I have to look for another solution.

Can you please suggest me any alternative?

Thank you for your timely response.