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ADC12DJ3200QML-SP: Question on CLK and SYSREF inputs

Michael Harmeyer
Prodigy 230 points
Part Number: ADC12DJ3200QML-SP
Other Parts Discussed in Thread: LMK04828, ADC12DJ3200, LMX2582

Concerning the CLK and SYSREF inputs.  We see the ADC12DJ3200 evaluation board has the two clock signals generated from LMK04828 and LMX2582.  It looks like TI wanted to be either time aligned or coherent.  Which is it?

  • 0
    TI__Mastermind 20541 points

    Hi Michael,

    There are 2 main ways for clocking the ADC12DJ3200 EVM.

    1. Onboard clocking. The LMK04828 provides a buffered copy of the onboard crystal oscillator (OSCout) to the LMX2582. By default, the LMX2582 is configured to generate the ADC device clock using this 100-MHz reference and the LMK04828 is used in clock distribution mode and provides the SYSREF and device clocks for the FPGA.

    2. External clock option. This option lets you bring an external signal to clock the ADC. With this option the clock signal to the ADC is split and first signal is feed into the ADC directly and second feed into the LMK. In this mode LMK is only used in distribution mode and it divide the clock signal to generate the FPGA ref clocks and SYSREF signal for the ADC and FPGA. LMX2582 is turned off in this configuration.

    The detailed explanation can also be seen in the users guide under Appendix B. Here is the link to the users guide.

    www.ti.com/.../slau701a.pdf

    Regards,

    Neeraj