ADC101S051-Q1: When delay time cannot be set for CS and SCLK.

Koji Hayashi92

Part Number: ADC101S051-Q1

Hi TI-team.

My customer cannot set the delay time for CS and SCLK due to the restrictions of the microcomputer used as the master. (CS and SCLK become Low at the same time.)

What are the harmful effects if the tSU time cannot exceed 10ns ?

Best Regards,

Koji Hayashi

over 4 years ago

0 Cynthia over 4 years ago

TI__Mastermind 24940 points

Hello,

Having CS and SCLK fall at the same time is acceptable. the set up time, t_su is the time that can elapse between CS falling and SCLK falling there after.

Thus this is an acceptable form of operation

Regards

Cynthia

0 Koji Hayashi92 over 4 years ago in reply to Cynthia

Mastermind 6970 points

Hi Cynthia-san

Thank you for response.

I understand.

Best Regards,

Koji Hayashi

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ADC101S051-Q1: When delay time cannot be set for CS and SCLK.