• State Resolved
  • Locked Locked
  • Replies 6 replies
  • Answers 2 answers
  • Subscribers 47 subscribers
  • Views 430 views
  • Users 0 members are here
Support feedback
Options
Options
Similar topics

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

LM98620: expression on datasheet

az
Prodigy 130 points
Part Number: LM98620

Hi there,

let me ask two questions about the datasheet expression below,

(1) In the Table 50 on page 50,

The Reg0x04 [3:2]bits are for Clock Rage Select. The frequency range mentioned is 10MHz-65MHz, but this device supports the frequency up to 70MHz. Would you tell me the register value for the 65MHz-70MHz.

(2) In the Figure 38 on page 45,

The SDO signal of SPI will be Hi-Z during write operation. But it is changed in the Figure 38 at the D7 data timing. What does it mean?

thank you in advance.

Regards,

  • 0
    TI__Mastermind 30205 points

    Hi,

    Let me check your question and feedback to you by Nov 16th.

    regards

    Shinya

  • 0
    TI__Expert 4940 points

    Hello,

    1) Reg0x04[3:2] = 00 will select 40MHz to 70MHz

    2) SDO will go HiZ  after the A0 clock and does not affect SDI received data .. The data bits  Tih and Tis should be >=5nS

    Regards,

    Costin

  • 0 in reply to Costin Cazana
    Prodigy 130 points

    Hello Costin,

    Thank you for your quick reply.

    1). OK, I'll try it.

    2). You mean that SDO in write mode will go Hi-Z after the first SDI 8bits arrived, because these bits indicate the R/W mode to the AFE.

    So that, dose the SDO keep "Low" or "High" until any command input (SCLK/SDI/SENB changed)? How does it work after any instruction finished?
    According to Figure 39, the SDO seems to be "Hi-Z" in the period except for actually outputting.

    Regards,

  • 0 in reply to Costin Cazana
    Prodigy 130 points

    Hello Costin,

    Thank you for your quick reply.

    1). OK, I'll try it.

    2). You mean that SDO in write mode will go Hi-Z after the first SDI 8bits arrived, because these bits indicate the R/W mode to the AFE.

    So that, dose the SDO keep "Low" or "High" until any command input (SCLK/SDI/SENB changed)? How does it work after any instruction finished?
    According to Figure 39, the SDO seems to be "Hi-Z" in the period except for actually outputting.

    Regards,

  • 0 in reply to az
    TI__Expert 4940 points

    Hi,

    The SDO is non HiZ mode after a read command, selected device driving D7-D0 on SDO. Rest of the time in read/write mode SDO is HiZ to allow multi device operation.

    Regards,

    Costin

  • 0 in reply to Costin Cazana
    Prodigy 130 points

    Hi,

    Thank you for your kind support.

    I understand and don't mind the unexpected change of SDO in the above Figure 38.
    Your answer makes me clear to use the SDO sharing with another device.

    Regards,

    az