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TSC2046: About ESD measures and latch-up phenomenon

Tsukui Yusuke
Guru 21930 points
Part Number: TSC2046

Hi,

Customer is conducting an ESD test of the application.
In the process, ESD invades from X ± and Y ± and latch-up occurs.

I think it is better to install TVS series and filters to take measures.
However, it is difficult for customers to mount components due to the board.

As an alternative, they were able to stop the latch-up phenomenon by limiting the current on the VCC line.
The current is limited to 5mA.
Could you give me some advice on the risks and precautions of taking such measures?

Best regards,
Yusuke

  • 0
    TI__Guru 62715 points

    Hello,

    The only reason the TSC2046 would experience similar results is if the absolute maximum ratings for the device are being violated in one way or another by conducting through the high/low-side protection cells and then triggering the absorption device inside the device.  While limiting the supply current perhaps at room temperature prevents the negative behavior, our recommendation is the same as yours to limit the input voltage to prevent the internal cells from ever conducting in-circuit and then they will not have issues.

    Please review the following training material for more information on EOS protection and while the information is based on op-amps it is applicable to ADCs as well.

    https://training.ti.com/ti-precision-labs-op-amps-electrical-overstress-overstress-protection