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DAC5670-SP: CLK is 500MHz and the signal is 220MHz

Danilo A.
Mastermind 27490 points
Part Number: DAC5670-SP

Hi Team,

Section 9.2.1 of the datasheet shows the DACCLK rate of 2GHz with signal output at 300MHz. A customer would like to know what will happen if the CLK is 500MHz and the signal is 220MHz?

Regards,

Danilo

  • 0
    Prodigy 90 points

    Hello.

      Just to add. In data sheet the CLK is said to have a minimum speed of 1GHz.

    Sincerely

      Klavs - The customer :D.

  • 0 in reply to klavs Rommedahl
    TI__Mastermind 18095 points

    The maximum clock rate is specified at 2.4 GSPS with a maximum of 1.2 GSPS per port but I did not see where the minimum clock speed was 1 GHz in the datasheet.  Can you highlight that more specifically.  Normally I would expect operation at at lower speed would be acceptable. 

    --RJH

  • 0 in reply to RJ Hopper
    Prodigy 90 points

    >>  Normally I would expect operation at at lower speed would be acceptable.

    so would I.
    Please look at page 11 in datasheet FDAC is minimum 1GHz maximum 2.4GHz

    Or did we missed some information somewhere ?

  • 0 in reply to klavs Rommedahl
    TI__Mastermind 18095 points

    Ahh, I see.  I believe the minimum specification referenced in Table 7.8 on page 11 of the datasheet references operation using the DLL (Delay Locked Loop).  With the DLL, there are timing/speed limitations.  You can bypass the DLL and manage the timing with proper set-up and hold times.  Operating at a lower speed like 500 MSPS should ease the timing requirements where operating without the DLL is satisfactory.

    --RJH

  • 0 in reply to RJ Hopper
    Prodigy 90 points

    Is there any guide lines to run this DAC without the DLL ? And is there any risk connected to this.

    How about timing in terms of precision and accuracy ? The DDR data rate is doubled to the clk so in short if we use DDR clk to run DACCLK then register clk would be 1/4 of the DDR datarate ? Thus we need to raise the DDR clk by 4 ? Or am I completly lost ?

    Sincerely

      Klavs.

  • 0 in reply to klavs Rommedahl
    TI__Mastermind 18095 points

    I think the guidelines are related to meeting setup and hold times outlined in table 7.8 of the datasheet.

    Reference section 8.3.2:

    In cases where it is not appropriate to use the DLL to manage the timing interface, it is possible to use fixed setup and hold values for DA and DB signals relative to the generated DLYCLK output when the DLL is held in restart. This is accomplished by asserting RESTART to logic high and using the timing input conditions for external timing interface with DLL in restart in the DLL Usage . When using external setup and hold timing, the user does not need to provide DTCLK. DTCLK should be biased to valid LVDS levels in that case (see Figure 2).

    I did not follow your clock approach exactly.  You would supply the normal sample clock at DACCLK.  The DTCLK is not used when DLL is not used.  The DDR clock or DLYCLK is div-by-4 compared to sample clock and samples on rising and falling edge.  The setup and hold times are "non-traditional" as seen in Figure 2 as the hold is a negative value.  Reference this paragraph in the same section.

    The setup/hold values are non-traditional, as they represent the setup/hold of an input to a generated clock (DLYCLK). Additionally, the setup/hold numbers represent delays that may be longer than the DACCLK or DACCLK/2 periods. To calculate the setup/hold values to the nearest adjacent DLYCLK transistion, the user must subtract multiples of DACLCK/2 periods until the setup is less than a DACCLK/2 period. The same amount can be subtracted from the hold time. These new setup/hold values will be frequency dependent.

    --RJH