AFE5805: DCLK and FCLK timing is incorrect

Kailyn Chen

Part Number: AFE5805
Other Parts Discussed in Thread: AFE5808, AFE5808A

Hello,

Please refer to the DCLK and FCLK timing of AFE5805, it is not compatible with the datasheet, how to affect the LVDS clock output？

While the correct timing of datasheet is as following:

Best regards

Kailyn

over 3 years ago

0 Xiaochen (Sean)Xu over 3 years ago

TI__Expert 6040 points

Kailyn,

something is wrong. i don't think the figures are from AFE5805. it might be from AFE5808 family.

Since you reported that AFE timing is not correct, we would like to see th eoutput of AFE signals directly. not from FPGA. because we don't know if any FPGA logic can add artifacts to the AFE outputs.

So far, AFE5808A and AFE5805 have been in production for over 10 years. We haven't seen that timings.

Waiting for your more info.

Thanks!

0 Kailyn Chen over 3 years ago in reply to Xiaochen (Sean)Xu

TI__Genius 9560 points

Hi,

Yes, you are right ,it should be the timing of AFE5808, not AFE5805.

Best regards

Kailyn

0 Xiaochen (Sean)Xu over 3 years ago in reply to Kailyn Chen

TI__Expert 6040 points

Kailyn,

please double check whether the output test pattern is correct.

Deskew Patten: When 2[15:13] = 010; this mode replaces the 14-bit ADC output with the 01010101010101

word.

This way, we can ensure the output is fixed.

Thanks!

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AFE5805: DCLK and FCLK timing is incorrect