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DAC38RF82EVM: no output

Part Number: DAC38RF82EVM
Other Parts Discussed in Thread: DAC38RF82, , DAC38RF80EVM

I'm testing DAC38RF82EVM with our A10 FPGA board. Where the FPGA code is from TI (DAC38RF82 84111).  

1. the DAC is set to 84111 with DAC clock at 6144, see attached

2. it's CMODE1 and SLAU671A has been followed, see attached

3. I've see the data flowing properly from Signal Tap inside FPGA (last on in attached)

4. observed proper 192MHz clock on J24 (PLL CLKout4)

However there are no output from neither DAC A nor B. 

The SERDES PLL0/1 are out of Lock.

Any idea? Thank you.dac84111_6144Mbps.pdf

  • New2day,

    1. On the quick startup tab, after doing a DAC reset, load default, load the DAC registers and sending data from the FPGA, make sure to click on the "Reset DAC JESD Core & SYSREF Trigger" button.

    2.What is the status of the SYNC signal? It should be high and staying high after doing the steps mentioned above.

    3. Are there any alarms present? Go to the Alarm Monitoring tab and click on "Clear all errors & read".

    4. Verify the DAC input clock is proper by operating the DAC in NCO only mode. Go to the Digital (DAC A) tab and set the data format to "Offset Binary" and enable the Constant Input. You should then see a 2140MHz tone out of DAC A. If not, there may be an issue with the input clock amplitude.

    5. Is the LMK providing the correct reference clock frequency to the A10 board?

    Regards,

    Jim  

  • Hi Jim,

    Since NCO only mode is supported, I have removed the EVM from our FPGA board to run stand alone test. 

    The EVM is in CMODE1, which is a 6144MHz PLL bypass mode (no PLL)

    1. 6144Mhz @16dBm apply to J1

    2. SERDES_CLK_SEL = 0 (DACCLK)

    3. SERDES_CLK_PREDIV = 4 (DACCLK < 9GHz and > 4GHz)

    4. SERDES_REFCLK_DIV = 2 or 4  (DERDES REFCLK is 768MHz or 384MHz)

    Were they right? 

    What's the SERDES CLK accordingly?

    5. ENDIVCLK = 1 (enable divided by 5)

    6. MPY = 5 

    7. NCO enable path AB

    8. NCO Freq 2140MHz

    9. set the data format to "Offset Binary" and enable the Constant Input

    Didn't see any output.

    SERDES PLL0 out of lock LED is OFF

    SERDES PLL1 out of lock LED is ON

    Observed 1536MHz @ - 13.5dBm from J4.

    Below are the printout from Quick Start Window:

    Current Serdes Lane Rate =7680.00MHz
    Maximum sample rate for Dual DAC,1 IQ pair,4 Lanes,8x interpolation is 9000
    Serdes Configured to Full Rate
    Serdes clock predivider = 4
    Serdes PLL Vrange = 1
    Serdes PLL Multiplier = 5
    HSDCPRO ini file: DAC38RF8x_LMF_841

  • Make sure the mixer is enabled and you click on "Update NCO" after you have entered the NCO frequency. All of your other settings are fine.  

  • Hi Jim,

    It's OK now and saw the NCO output. Forgot to enable the mixer. 

    Thank you very much.

  • Hi Jim,

    For seeing the NCO output,

    1. I could not click CONFIGURRE DAC button after reset and load default.

    Why is like this? 

    Would it be possible to see the NCO only output after CONFIGURRE DAC? 

    2. Without CONFIGURRE DAC, I can only see DAC A but not DAC B

    Was it right? 

  • The reset does not set all registers to know values so you should always load the default values then configure the DAC.   

  • Hi Jim,

    Yes, it's always a RESET following load default and then CONFIG DAC with

    1. 6144MHz clock (CMODE1 at 16dBm, 16.5dBm or 17dBm)

    2. single or dual DAC

    3. 1 IQ pair

    4. 4 Lanes

    5. 16x (single) or 8x (dual)

    So that the Lane rate = 3840Mbps (single) or 7680Mbps (dual). 

     

    When plug the DAC38RF80EMV to our FPGA board,  observed the SYNC from DAC is up (HIGH) and data flowing properly at transport layer, link layer and PCS layer. 

    However there is no output with all Lane read_empty: FIFO is empty. 

    The firmware is A10_DAC38RF82_7p68G_84111 from TI. Which says for DAC38RF82 and the EVM I have is DAC38RF80EMV and selected as DAC38RF83 due to the GUI. 

    Any suggestion? Thank you very much.

  • I am guessing your DAC PLL is not locked. Follow the steps in the attached example to get the DAC PLL locked and verified. Do not use the DAC clock frequency and reference clock frequency shown in this attachment is they may be different from your settings.

    DAC38RF82_6400M_PLL_300M_ref_82380.pptx

  • Hi JIm,

    External clock mode (CMODE1) is used. Which means DAC PLL bypassed (not enabled). 

    DAC38RF8xEVM user guide (slau671a) was followed. 

    Thank you.

  • In your other post, you mentioned using the Arria 10 example. This uses the DAC PLL so I am confused about your setup. Lets focus on only one configuration.

    Please provide the following:

    DAC CLK freq

    SYS Ref Freq

    K value

    LMFS setting

    Interpolation factor

    serdes rate

    Lane mapping to FPGA

    1 IQ or 2 IQ

    Are you following the attached document?

    Regards,

    Jim

    A10 DAC38RF82 7p68G 84111 Reference Design User Guide.pdf

  • Hi JIm,

    DAC CLK Freq = 6144MHz

    SYS Ref Freq = 4.8MHz

    K value = 20

    LMFS setting = 84111 [as the A10 firmware from TI (84111)]

    Interpolation factor = 8x

    SERDES rate = 7680Mbps  [as the A10 firmware from TI (7p68G)]

    Lane mapping to FPGA is DAC RX[7:0] pins to FPGA TX[7:0]

    1IQ (since LMFS = 84111)

    Yes, A10 DAC38RF82 7p68G 84111 Reference Design User Guide.pdf is followed other the clock mode, it's CMODE1 (external clock) in my set-up. 

    Was it not supported with using A10 firmware from TI? 

    I got all PLL locked inside FPGA side with CMODE1 (external clock), SYNC from the DAC is up and data is flowing properly on FPGA side too.

    I can try enable the DAC PLL.  

    Thank you very much.

  • new2day,

    If you cannot get your DAC board to work following the attached slides using the TSW14J56EVM, I would suggest you request a replacement. Make sure jumper JP10 is installed. I did this test with an external clock of 6144MHz connected to J1, and used all of your settings. Both serdes PLL's locked. You will have to click on them to update their status. No alarms or errors were reported.  

    Regards,

    Jim

    DAC38RF80_8411_6144_Fs .pptx

  • I've tried with DAC PLL enable as in A10 DAC38RF82 7p68G 84111 Reference Design User Guide.pdf

    There are still no outputs and more error messages:

    Now two more errors about write and read error besides FIFO empty. 

    Questionwould A10 firmware from TI work for DAC38RF80EVM? Thank you.

  • Hi Jim,

    I've tried with TSW14J56EVM by following DAC38RF80_8411_6144_Fs .pptx, both SERDES PLL0/1 are still Out of Lock - JP10 jumper is installed. 

    There are outputs though. 

    I like to check how to replace a new from TI.

    Was it free of charge?

    Can I replace it with DAC38RF82EVM instead?

    Thank you very much.

  • new2day,

    If you bought this from a distributor, you will have to work with them to get a replacement. If you bought it from the TI Store, the following link has the details and a link to the form to start the return process.  Once you are on the returns and refunds page of the TI Store look for the hyperlink which says: TI store customer support form. You can request a DAC38RF82EVM but not sure they will provide one.

    Regards,

    Jim

     

    www.ti.com/.../ti-store-order.html