Other Parts Discussed in Thread: DAC38RF82, , DAC38RF80EVM
I'm testing DAC38RF82EVM with our A10 FPGA board. Where the FPGA code is from TI (DAC38RF82 84111).
1. the DAC is set to 84111 with DAC clock at 6144, see attached
2. it's CMODE1 and SLAU671A has been followed, see attached
3. I've see the data flowing properly from Signal Tap inside FPGA (last on in attached)
4. observed proper 192MHz clock on J24 (PLL CLKout4)
However there are no output from neither DAC A nor B.
The SERDES PLL0/1 are out of Lock.
Any idea? Thank you.dac84111_6144Mbps.pdf