DAC8831-EP: power on/reset default state for VREF output

Hi Michael,

That could be a problem in your application, as it will start at zero code.  Would it be possible disable your reference voltage at startup? Some feature an enable pin.

Thanks,

Paul

Paul, 

Thank you for the feedback. 

To be clear - it would be possible to hold off the VREF until our commanding FPGA boots and provides a non zero value?

Do we have any "equivalent" parts with an enable pin?

Ok I think we should be able to sequence the VREF I just wanted to make sure that there were no caveats doing so. I would plan on bringing the part up without VREF then writing a non 0 initialize value then bringing VREF on correct? What would be the voltage on the output without a VREF 0V or Z id presume?

I would have a similar behavior to the output of the reference.  If the reference is 0V when it is disabled, then you should see that on the output.  If the reference is high-z, you can imagine the DAC would look like that same high-z node but with a series resistance on it.  I recommend they add medium resistor value to ground from the reference if it is high-z.  Maybe 10kΩ