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ADS8353: Writing and Reading the CFR register returns 0x2ff8 instead of what I sent (PIC24)

Part Number: ADS8353

I am starting to work with the ADS8353 and am not getting what I expect when I try to set the CFR register and read it back.  Based on several forum posts here, I think I am doing it the same way, so clearly I am missing something simple.

My understanding is to write a register, you just put it out as the first 16-bits followed by 32 more clocks.  Using the CCS PIC24 compiler, this looks like this:

    output_low (SlaveSelectPin);
    delay_us (1);
    spi_xfer (SPI2_MODE0, ConfigRegister, 16);
    spi_xfer (SPI2_MODE0, 0, 32);
    output_high (SlaveSelectPin);

Using a Saleae analyzer I can confrm I see the value written out to the wire in the first two 8-bit bytes, followed by 0's for the next 4 bytes (total of 48 bits).

When I try to read a register, I follow the same examples I found elsewhere in this forum:

1) Frame (F) - one empty frame of at least 48 CLKs

2) Frame (F+1) -To readback the user-programmable register settings, the appropriate control word should be transmitted to the device during frame (F+1)

3) Frame (F+2) - During frame (F+2), SDO_A outputs the contents of the selected user-programmable register on the first 16 SCLK falling edges.

In the CCS compiler, it looks like this:

    // Frame (F) - one empty frame of at least 48 CLKs
    output_low (SlaveSelectPin);
    delay_us (1);
    spi_xfer (SPI2_MODE0, 0, 16);
    spi_xfer (SPI2_MODE0, 0, 32);
    output_high (SlaveSelectPin);
    delay_us (1);

    // Frame (F+1)
    // To readback the user-programmable register settings, the appropriate
    // control word should be transmitted to the device during frame (F+1)
    output_low (SlaveSelectPin);
    delay_us (1);
    spi_xfer (SPI2_MODE0, Value, 16); // Write 16 bits.
    spi_xfer (SPI2_MODE0, 0, 32);     // Pad to 48 CLKs.
    output_high (SlaveSelectPin);
    delay_us (1);

    // Frame (F+2)
    // During frame (F+2), SDO_A outputs the contents of the selected
    // user-programmable register on the first 16 SCLK falling edges
    output_low (SlaveSelectPin);
    delay_us (1);
    Value = spi_xfer (SPI2_MODE0, 0, 16); // Write 16 bits.
    spi_xfer (SPI2_MODE0, 0, 32);     // Pad to 48 CLKs.
    output_high (SlaveSelectPin);

I write the CFR by sending 0x8640 padded to 48-bits.

To read, I send:

1) 48-bits of 0

2) 0x3000 ...padded to 48-bits of zero

3) 48-bits of 0's reading the response in the first 16.

But I get back 0x2ff8 -- and the start bits of 0010 (0x2) which looks like it is giving me a REFDAC_B register instead of CFR (which should start with 0011 - 0x3).

My analyzer shows things populated in the expected areas to read DAC A (0x00 0x00  DACA DACA xx xx) so it appears I am talking to the part. I expect I am missing something in setting the CFR.

Any clues on what I have missed in the data sheet?

Thanks, much.

  • Additional notes.  The value of 0x2FF8 I get back appears to match what REFDAC_B would return:

    0x2FF8

    111111
    54321098 76543210
    -------- ========
    00101111 11111000
    |   |         000 = Must be set to 0 (default).
    |   1111 11111    = Data to program the individual output voltage.
    0010              = REFDAC_B

     

    Reg         Write   Read Back
    ----------- ------- ---------
    CFR         1000    0011
    REFDAC_A    1001    0001
    REFDAC_B    1010    0010

     

  • Hi Allen,

    Everything you provided looks correct.  There may be a timing violation.

    You have a 1uS delay between /CS falling edge and the first CLK, but no intentional delay between the last clock and /CS rising edge.  Please verify that there is a minimum of 15nS between the 48th CLK falling edge and the rising edge of /CS.

    Also, the maximum CLK frequency is 20MHz; please verify that you are meeting this requirement.  Finally, the ADS8353 captures data on the SDI pin and launches data on the SDO pin on the falling edge of CLK. Please make sure your SPI protocol is compatible with this requirement.

    A capture of the write and read operations may help answer these questions.  Can you attach the Saleae file? 

    Thanks!

    Regards,
    Keith Nicholas
    Precision ADC Applications

  • Keith Nicholas said:

    Finally, the ADS8353 captures data on the SDI pin and launches data on the SDO pin on the falling edge of CLK. Please make sure your SPI protocol is compatible with this requirement.

    Thanks, Keith. The moment I read "falling edge" I realized I had something set up wrong.  I switched my SPI code to Mode 1 and adjusted the Saleae and now I get much more plausible results. But I do have a question about the first four bits returning from the CFR read:

    ADS8353WriteRegister (0x8460) - 1000 010001100000
    ADS8353WriteRegister (0x9f00) - 1001 111100000000 <- just something I can easily recognize when I read it back.
    ADS8353WriteRegister (0xaf00) - 1010 111100000000 <- just something I can easily recognize when I read it back.

    ADS8353ReadCFR () - 0x0460 - 0000 010001100000

    ADS8353ReadREFDACA () - 0x1f00 - 0001 111100000000

    ADS8353ReadREFDACB () - 0x2f00 - 0010 111100000000

    ADS8353ReadDACA () - 65535
    ADS8353ReadDACB () - 65535

    REFDACA and REFDACB come back with 0001 and 0010 matching the readback in Table 10.  But the CFR returns 0000 (then the rest of the expected bits I configured).

    Should I be expecting 0011 for the start of the CFR readback?

    Thanks, much.

  • Hi Allen,

    It sounds like you have the interface working.  The CFR register address is 00b, so I think the first four bits will read back 0000b.  I found at least one other customer that sees the same behavior.

    I would check this on an evaluation board, but unfortunately, I do not have one at this time.

    Regards,
    Keith 

  • Your quick response was most appreciated. Thank you.  We have five TI SPI chips on this new design, but I think I got those going. If not, I'll be back ;-)

  • If you have any more questions, please do not hesitate to post to the forum.

    Regards,
    Keith