ADS62P25: Interfacing (LVDS) of ADC with the FPGA

Tensil Sebastian

Part Number: ADS62P25

Hello Together,

Am using ADS62P25 High speed ADC I want to interface the LVDS output of the ADC to my FPGA.

FPGA am using is Arria 10.

The Common mode voltage of the ADC is 1.5V and the common mode voltage of the FPGA is 1.25V Will there be any problem if I interface both directly.

In the attachment please see the LVDS level of the FPGA.

Please let me know if any more information is required.

Regards,

Tensil Sebastian

over 3 years ago

0 jim s over 3 years ago

TI__Guru* 91947 points

Tensil,

Since the ADC common mode exceeds the max allowed by the FPGA, you will need to correct for this by either adding a level shifter or use AC coupling. If you decide to use AC coupling, you may need to add bias resistors based on the FPGA internal biasing. I would suggest checking with the Intel forum for more help with this.

Regards,

Jim

0 Tensil Sebastian over 3 years ago in reply to jim s

Prodigy 170 points

Hello Jim,

Thanks for the response.

In the ADC datasheet two common mode voltage information is mentioned.

In one place common mode is mentioned as 1.5V and other place it is mentioned as 1.2V.

Which one do i need to consider when I am interfacing with the FPGA (LVDS mode)

Please find the details in the attachment.

Regards,

Tensil Sebastian

0 jim s over 3 years ago in reply to Tensil Sebastian

TI__Guru* 91947 points

Tensil,

After looking at the data sheet in more detail, it appears the output data common mode is 1.2V and should work fine with the FPGA interface. The analog input has a common mode of 1.5V, which was adding to the confusion. These are the two common mode voltages you are seeing and they are not related.

Regards,

Jim

0 Tensil Sebastian over 3 years ago in reply to jim s

Prodigy 170 points

Thanks Jim

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ADS62P25: Interfacing (LVDS) of ADC with the FPGA