Part Number: TSW14J56EVM
I have received the boards ADS54J60EVM + TSW14J56EVM. I am making a data capture module. In particular, I would like to connect an Arria V Altera FPGA to the ADC via the JESD204B interface.
1) Would TI be able to send me the FPGA Verilog or VHDL design files that are used for the evaluation kit, in order to serve as a reference design? Also is it possible to get the reference design or diagram used in the connections between the Altera V GZ family FPGA (5AGZME1E2H29C3N) with the DDR3 Memory (870-3TR16512AL125KBL).
2) We can’t get the raw data from the hsdc pro, it has only functions available like get_fft_data and ADC_Save_Raw_Data_As_Binary_File. So the data we are getting from the HSDC needs to be converted back to normal raw data externally which is just a waste of time and memory. Do we have any such command in the hsdc software to just get the raw data and save it in some file for analysis?
3) The number of samples we can display is limited by the memory available on the TSW EVM. Though we can go higher upto 1073741824 16 bit samples. But we never run the HSDC Pro GUI (for TSW) to capture so many data for each capture. It does not mean memory is too small. It could cause the GUI running very slow or too slow from memory to USB and also from GUI software itself. So effectively it can capture about 65536 captures. For higher number of samples captured, we need to use some other evaluation kit. Can TI recommend any such evaluation kit?
4) The Altera device on theTSW14J56EVM is loaded everytime after power up using the HSDC Pro GUI. There is no factory installed firmware. For loading our own Firmware, we either need to make some changes to the original firmware provided by TI (which can damage the TSW board) or we can simply use the Intel Quartus II to program the Altera FPGA. For programming the Altera FPGA, we need connect a USB ByBlaster to the TSW14J56 JTAG and should be able to auto detect the device connected to validate the JTAG chain is working. Then can program accordingly. Is this information correct or do we need to make more changes to it?
5) This is more of like a doubt. HSDC Pro GUI utilizes a DLL and a set of API's to communicate from the GUI to the TSW14J5x via a Cypress FX3 USB 3.0 device. The data transfer speed (as mentioned in the hsdc user guide) is 2Gbps. Now, we are having the data output from the ADC at max 10 Gbps, and 12.5 Gbps is for the FPGA. So wont it just hinder the performance of the transfer rate?
6) Also, while looking at the hsdc folder, I came across three major files- ini (for ADC), .rbf (for FPGA firmware) and mif (that specifies the initial content of a memory block that is the initial values for each address. This file is used during project compilation and/or simulation; it helps in the configuration of the lane rates and PLL used during the ADC-FPGA communication). This is all I could understand while reading the codes given in the C:\Program Files (x86)\Texas Instruments\High Speed Data Converter Pro\14J56 Details\ADC files. Can TI guide me more on this and the way to view the .rbf and .mif files?
