Other Parts Discussed in Thread: LMK04828, ADC32J45, , DAC37J84, ADC34J24
To change the ADC / DAC from serial LVDS to JESD204B, our customers are considering a signal chain by combining the following products.
/ ADC32J45 or ADC34J45
However, in the ADC32J45 / ADC34J45 data sheet
SYSREF: The input circuit is unknown, and the circuit cannot be examined because the VCM range and amplitude range are not described.
SYNC: The input circuit is unknown, and the circuit cannot be examined because the VCM range and amplitude range are not described.
Customer plans to DC-couple because SYSREF is a pulse signal.
The LVDS output range of the LMK04828 is as follows.
Vodiff: Typ: 395mV * Range not shown
Vocm: Min 1.125V --Max 1.375V (Typ: 1.250V) * Termination 100Ω
Is DC coupling possible? (Termination is 100Ω)
Since the range of Vodiff is unknown, please let me know if there is any problem.
Evaluation board: Why is the ADC34JXXEVM outputting from LMK04828 with LCPECL?
I think it's easier to terminate 100Ω using LVDS.
Please let me know if there is any problem with this method.
Customer wants the SYNC signal to also be DC coupled with the LVDS output of the FPGA.
The LVDS output range from FPGA is as follows.
Vodiff: Min 247mV --Max 454mV (Typ: 350mV) * Termination 100Ω
Vocm: Min 1.000V --Max 1.425V'Typ: 1.250V) * Termination 100Ω
Is DC coupling possible under these conditions? (Termination is 100Ω)
There is an E2E answer in the past at the following URL, but the data sheet has not been revised.
We are competing with ADI's solution and we need TI's help to D-IN.
It would be helpful to have a detailed example of a signal chain guaranteed by TI.