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ADS7066: Understanding Tacq to design front end drive circuit

Part Number: ADS7066


I am designing a front end drive circuit for the ADS7066 to read ~6 photodiodes in parallel. The level of illumination on my photodiode changes every ~0.0316 seconds, giving me an input frequency of ~32Hz. 

That being said, I understand that it is necessary to oversample to get a reliable result, so I (arbitrarily) applied a factor of 50 and assumed a sample rate of 1.6kSPS. As I mentioned, I will be using ~6 of the ADC channels, so the overall sample rate would be 9.6kHz (I believe).

I am trying to figure out what size of Rfilt and Cfilt I need on my driver. I used the SAR ADC front-end driver design precision labs video as well as the calculator tool, but where I'm getting hung up is the Tacq. From what I've gathered, my Tacq will be:

Tacq = 1/fsample - tconvmax = 1/(9.6kHz) - 3200ns = ~100us

Using the calculator tool, this gives me a Rfilt minimum of 5.135kOhms. This seems very large to me. My question is, am I thinking about this wrong? Did I arrive at my Tacq incorrectly?

Thank you very much for your insight,

Austin Allen

  • Hello,

    It seems that you have calculated the acquisition time correctly for this device. 100us seconds is quite a long acquisition time, This is probably why other aspects are so relaxed. 

    simulating the circuit can help to see how it would respond, and build confidence before physically building the circuit. There is a TINA Spice model available for the ADS7066. 

    I would like to share with you other resources available as well, there is analog cookbook available that has short descriptions on specific circuit configurations for op amp , ADCs, DACs and more.