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A question for a verilog-firmware of TSW1200EVM and ADS4226

Lim Euncheon
Prodigy 160 points
Other Parts Discussed in Thread: ADS5463, ADS4226EVM, ADS5282

Hi,

I received TSW1200 Source Serial v1p5 from Richard.

The problem is I need to modify the firmware code.

I want to know follwoing questions:

1) are ads5463.ucf, ads 5463_ddrif.v, ads5463_toplevel.v and other verilog codes compatible to ADS4226EVM?

2) is the PROM file generated from the TSW1200 Source Serial v1p5 exactly same with the bit file of TSW1200 in my hand?

3) I ordered a DLC9G programming pod. Is that all to store new FPGA programming bit file?

4) What source code should I modify to change the raw data? For example, I want all data to be deducted 10 from the original value.

5) I need to connect an external DAC through SPI. Are there free pins that I can send some signals after a cycle of ADC finished?

6) I found following line in ads5463.ucf, is that valid for ADS4226EVM?:

TIMESPEC TS_ClkDDRp = PERIOD "ClkDDRp" 2.5 ns HIGH 50%;  #ADS528x at 800Msps

7) Is there a programatic way to change the AC-coupling mode into the DC coupling one as we can the same thing in use of an oscilloscope?

Sorry for my too much questions.

Regards,

Euncheon

  • 0
    TI__Mastermind 29220 points

    Hi,

    I looked through my email, and i did send you the source code for the serial data formats on July 18 because your request was appended to a posting about the ADS5282 EVM which is a device that has a serial data format. 

    The TSW1200 can support EVMs with ADCs that have either a serialized data format or a parallel LVDS DDR data format, depending on the position of jumper J11 as described in the User Guide for the TSW1200.  The eeprom on the TSW1200 is large enough to hold two bit files for the FPGA and jumper J11 selects whether the bit file to the FPGA is taken out of the lower half of the eeprom or the upper half of the eeprom.

    1) No, the source code you have is not compatible with the ADS6226 EVM.  You need the source code for the parallel DDR data formats.

    2) The code for the eeprom is formatted from two bit files (one for the serial format and the other for the parallel format) by the Xilinx impact utility into an mcs file, and this is the file programmed into the eeprom.  The source code you have would generate the exact bit file as one of the two bit files that went into the mcs file.  The other source code would generate the other bit file that went into the eeprom.

    3) I use a DLC9 programming pod, but mine does not have the G printed on it.  But yes, this should work fine.

    4) Once you get the right source code for the EVM you are using, then there are about 5 levels of file hierarchy of the ADC interface where you could go in and modify the Verilog, or you could go to the source code for the buffer memory and identify the data busses from the ADC interface code and make the change there.  I'd consider making the change in file ads5463_ddrif.v.

    5) After all the connections were made to the eight banks of header posts, there were very few unused pins left in the FPGA.  But these header posts are there to output the sample data to a logic analyzer if you don't wish to use the campture memory to the PC.  You could redefine the use of these pins for something else.

    6)There would be a similar constraint in the ucf for the parallel data format source code.

    7)  I do not understand the question.  If you are talking about the input circuit on the ADC EVM between the SMA connector and the data converter, then this could only be modified by unsoldering and soldering components.

    I'll send the source code for the parallel DDR data formats shortly.

    Regards,

    Richard P.

  • 0 in reply to Richard Prentice
    Prodigy 160 points

    Hi,

    In addition to the previous questions, I need more specific explanation for some questions.

    In second question, you mentioned that the two bit file should be merged into one mcs file.

    Do you mean generating files for TSW1200 Source Serial v1p5 and TSW1200 Source Parallel DDR ver1p6.zip into one mcs file is required?

    If so, what is the order of files?

    In seventh question, I have an AC+DC signal ranged from 0 to 500 mV but the ADC shows nothing. I supposed that ADS4226EVM uses AC coupling input mode

    so that the AC+DC signal cannot be detected. The ADC results seems to remain in near 0 value.

     

    Regards,

    Euncheon

  • 0 in reply to Lim Euncheon
    TI__Mastermind 29220 points

    Hi,

    Yes, the two bit files that you listed are formatted into one mcs file.  The Xilinx impact utility is used to format them into the mcs file.  The PROM File Formatter flow is chosen.  Then revisioning is chosen with 2 being the number of revisions.  The xcf16p eeprom size is chosen.  Then the serial bit file is inlcuded first followed by the parallel.  If these were chosen in the wrong order then the position of jumper J11 would simply be reversed.  And do not choose compression.

    Yes, it sounds like the AC coupling aspect of the transformers are preventing your signal from getting through.  You would need to consult the User Guide for the EVM and the schematics for the board to decide how to configure your input circuit.  The transformer footprints are such that if you unsolder the transformer you could solder in a zero ohm resistor across the pads from input to output to bypass the transformer footprint completely.  And there is space provided for soldering down another SMA connector for inputs for both sides of a differential input.  (Such as if you are bringing in a differential signal from an amplifier eval board.)   Finally, there is a differential amplifier on the EVM for each of the channel inputs, but by default the output of the amp is AC coupled to the ADC input.  You would need to design and solder the desired circuit between the amp and the ADC.

    Regards,

    Richard P.