SNR data required for the ADC ADC16DV160 at 1100MHz

Hi Jim,

     Thanks for your SNR vs jitter data at 1100MHz.

1) Do you have any recommended circuit (clock source / Jitter cleaner) to achieve <150fs Clock source jitter to achieve the SNR around 60dB by using your ADC part ADC16DV160?

2) Also we need to know , Whether your single channel ADC: ADC16V130 (130MSPS) also will give the same SNR performance for the above mentioned clock jitter values?

Regards,

Sugumar K

Hi Jim,

    We are planning to use your ADC ADC16DV160 for under sample our RF signal 1100MHz at 160MSPS.

In the above table you have mentioned that the ADC SNR [dBFS] is 60.59dB for Clock Total rms Jitter [fS] of 150fs @-1dBFS input level. It is ok for us.

Also we have one more question, when we apply low input signal around -65dBFS then the clock jitter impact will be very less even though at our frequency of 1100MHz.

May I know the ADC SNR value at the below input power levels while under sampling our RF signal 1100MHz at 160MSPS.

Input Signal level     ADC SNR

-65dBFS                      ????

-70dBFS                      ????

-75dBFS                      ????

Regards,

Sugumar K

Hi Sugumar

Many of us are out of office for the US Thanksgiving holiday returning on Nov 30th.

The earliest I may be able to look into these estimates is Saturday Nov. 28.

Best regards,

Jim B

Sugumar,

The SNR performance at the amplitudes you are curious about (-65dBFS and below) are so low that the SNR performance will be very close to the base SNR of the device with no jitter impact, 78dBFS.

Regards, Josh

We are planning to ADC part ADC16DV160 at 1100MHz signal for the full scale signal of +10dBm (50Ohm) in normal operation.

We are planning to use your recommended circuit as per you datasheet (Figure 29) at Page No: 18. It is mentioned in the Absolute Maximum Ratings of Voltage at CLK, Vin Pins -0.3V to (VA1.8+0.3V) and mentioned (Not to exceed 2.35V).

1. Now what should be the maximum RF input in dBm level to this ADC input transformer?

2. The maximum voltage 2.35V mentioned is with respect to GND or common mode voltage?

Request you to explain the same with maximum input level to the ADC for our operation.

Regards,

Sugumar K

Hi,

     We need to calculate the Cascaded noise figure with our RF Receiver module and ADC to estimate the system Noise figure. For that kindly provide the ADC ADC16DV160 noise figure (dB) or Noise-Spectral-Density (dBFS/Hz) to proceed us further.

Our RF Frequency is 1100MHz and sampling is 160MSPS for your reference.

Regards,

Sugumar K

Hi Josh,

    We are planning to use ADC16DV160 ADC input as 50Ohm for the full-scale of 2.0Vp-p configuration which is corresponds to +10dBm RF input power.

NSD = FScale - SNR - 10*log10(Fs/2) = +10 - 78 - 10log10(160e6/2) = --147.0 dBm/Hz

The NF at room temp can then be calculated as

NF = -147.0 - (-174) = 27.0 dB

As per the above configuration we are planning to proceed to work and we will verify our cascaded noise figure for our system.

Is there any issue in this above configuration?

Regards,

Sugumar K

Calculation looks good

Cheers, Josh

We are planning to use the ADC input as 50Ohm differential to operate maximum input power of +10dBm for corresponding 2Vp-p.
So kindly suggest a application circuit with ADC input components for our operating frequency of 1100MHz for 50Ohm differential input load at ADC.

Also request you to suggest a low jitter clock source application circuit/ parts for our sampling frequency of 160MHz for better ADC SNR performance at our operating frequencies of 1100MHz.

Regards,
Sugumar K

Can we use the Mini-circuits 1:1 Balun transformer TC1-1-13M+ at ADC input for our high frequency RF input signal of 1100MHz sampling at 160MSPS.

Also Request you to provide the application circuit for the same for 50Ohm ADC input impedance to meet the maximum input power of +10dBm.

Sugumar,

Yes, you can use the TC1-1-13M+, or the MABA-007159 (similar device from MA/COM). They will both yield similar performance. Anaren's BD0810J50100AHF looks like it might do very well as well. You can do something like one of the circuits below.

There will be a trade-off between dynamic distortion performance (H2, H3) and Input bandwidth which depends on how you set the value of the capacitors at the input of the ADC. They are meant to provide charge to dissipate the ADC's charge kickback, but they do limit the bandwidth. I think you must experiment to find the optimal tradeoff point.

Our LMK (LMK040xx, LMK0480x) clocking products are a good match-up with this device. 

Regards, Josh

Hi,

As you said above without any jitters the SNR very close to the base SNR of the device 78dBFS. But we are doing ADC sampling at 160MSPS whereas our data bandwidth is only 16MHz. As per the FFT process gain, 10×log(Fs/(2XBW)) expecting additional processing gain of 7dB. So the final ADC SNR value expected is = 78dB (SNR) + 7dB (processing gain) = 85dB SNR.
But we need to know whether we are able to see this SNR before DDC in FPGA or in the RAW ADC output itself?

Regards,
Sugumar K

Sugumar,
When you observe the data at the output of the ADC, you will observe the signal plus the base thermal noise (limits base ADC SNR to 78dBFS) plus noise due to clock jitter. Processing gain occurs during filtering which occurs in your DDC. Therefore, your signal path will not have SNR=85dB until after the DDC.

If you are just analyzing noise performance of the ADC and want to include processing gain, then you can take the ADC output data, calculate the FFT, and then do a power ratio calculation using only the spectrum band of interest.

Regards, Josh