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DAC5652 Interleaved Mode SELECTIQ Timing Problem

Po-Chen Lin
Prodigy 150 points
Other Parts Discussed in Thread: DAC5652

Hi,

  I'm using DAC5652 to generator a waveform in every clock cycle, the CLKIQ&WRTIQ are 20MHz in phase.

My problem is when I fixed the SELECTIQ signal(pull-down or pull-high), I can't get the waveform from the both A&B channel.

But when I start switching the SELECTIQ, I got the waveform, what's it?

Another question, what's the "IQ" means?

  • 0
    TI__Genius 12965 points
    Hi Po Chen,

    IQ in this case just means A or B. This DAC can be used in some application that use quadrature modulation (IQ modulator).

    In single bus interleaved mode the SELECTIQ needs to be toggled as per the data sheet on page 14. IF SELECTIQ is not toggled then only 1 side of the data latches will get the data, the other side will not latch any data. In this instance you should just get output on 1 DAC.

    Keep in mind you must be providing interleaved A,b data on the DA input. The output rate will be at CLKIQ/2.

    Ken
  • 0 in reply to Ken C
    Prodigy 150 points
    Hi Ken,
    But now I get nothing neither CH-A nor CH-B, when SELECTIQ is set to be "not swing", this makes me very confused.

    About the output rate, do you mean if the CLKIQ is 20MHz, I will only get 10 MSPS?
  • 0 in reply to Po-Chen Lin
    TI__Genius 12965 points
    Hi PoChen

    When you say not swing - what level is it at? Is it held high or is it held low?

    Also what data are you presenting to the A,B interleaved DA input and are you seeing the expected output on A/B when SELECTIQ is toggling? You should see every other sample on the input go to A and B.

    Since all of the data is coming on DA, and you split this data to A and B, then the input datarate will be 1/2 at the DAC output.

    Ken.
  • 0 in reply to Ken C
    Prodigy 150 points

    Hi Ken,

      Following is my timing char, probed from FPGA.

    I use RESETIQ to sync CH-A and CH-B.

    If I only want to present CH-A, I have to switch the SELECTIQ(the third signal, named AB_SELEC) as following figure.

    If I set SELECTIQ to Hight, I will get nothing from CH-A ouput.

  • 0 in reply to Po-Chen Lin
    TI__Genius 12965 points
    Hi Po Chen,

    When SELECTIQ is high do you get anything on the other output channel?

    Ken
  • 0 in reply to Ken C
    Prodigy 150 points
    Hi Ken,
    When SELECTIQ is always high, there is no output waveform on the both channels.
    When SELECTIQ is always low, there is no output waveform on the both channels.
  • 0 in reply to Ken C
    Prodigy 150 points

    Hi Ken,

      And I found the DAC will latch only the first data out on CH-A when SELECTIQ always stay high,

    when SELECTIQ stay low the first data will be generate on CH-B also.

  • 0 in reply to Po-Chen Lin
    TI__Genius 12965 points

    Hi Po Chen,


    Let me clarify with the design team and get back with you.

    Ken.

  • 0 in reply to Ken C
    TI__Genius 12965 points
    Hi Po Chen,

    I spoke with the designer and it seems that the SELECTIQ state is used to latch in the data from DA into CHA and CHB. Without the SELECTIQ toggling the data will not be latched in properly and the samples going to the output DAC will not be updated. It will hold the last value latched when SELECTIQ last toggled.

    If you wish to hold 1 of the values constant on CHA or CHB you will need to do this in the FPGA by placing the appropriate value in the CHA or CHB time slot on the DA bus.

    Ken.