This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

  • Resolved

TSW1400/ADS5483 DATA CAPTURE PROBLEM

Genius 4430 points

Replies: 22

Views: 3682

E2e,

We have a customer evaluating a ADS5483 using the TSW1400.   When doing a data capture an error occurs which says "Read DDR to file time-out".  How this be corrected?

Thanks for your help.

Regards,

John Wiemeyer

  • Hi

    The most common cause for a timeout error is that the FPGA is not getting a clock from the data converter, which may be caused by either a misconfiguration of the ADC or the ADC EVM not getting a clock in the first place.   When the capture button is pressed, the TSW1400 FPGA will clock sample data into memory using the clock from the ADC until the requested number of samples have been caught.  If there is no clock, then the requested number of samples cannot be caught before the GUI times out.  (Although the exact wording of the error message might lead one to think the data was caught inthe DDR2 memory stick on board but timed out getting the data up to the PC.  But I dont think the error messages really make that fine a distinction on where the error might be.)

    The TSW1400 has a bank of 8 LEDs on it to indicate the status of the FPGA, and one of the LEDs in the middle the bank (USER_LED3) lights when the FPGA is locked onto the LVDS data clock from the ADC EVM.  If this LED is not lit then there is no clock from the ADC to the TSW1400.

    Since the ADS5483 does not have registers to be programmed through SPI and thus no SPI GUI for this EVM, then having the ADC misconfigured is not likely.  Check to see that the clock into the EVM is valid, and if it looks to be valid, then possibly check with an oscilloscope for the presence of the clock into the ADC and the presence of the clock (called DRY I believe) out of the ADC.  And of course check that the EVM has power supplied.

    If one of these things do not solve the problem then we will have to dig in a little deeper and see what is gong on.

    Regards,

    Richard P.

  • In reply to Richard Prentice:

    Thanks for that. We found that the USER_LED3 is off meaning there is no clock coming from the ADS5483EVM. Worse than that no LEDs on the board a lit except for the power LED.
  • In reply to WhiteHorse:

    Hi,

    If none of that bank of LEDs are lit then I would suspect the FPGA does not have its bit file loaded, but in that case the GUI should not let you click the capture button.  Perhaps i could see a screenshot of the HSDCPro - i would be looking for the firmware name to be visible in the lower right corner and saying ADC_BYTE_WISE_1CH as the name of the firmware loaded into the FPGA.  The user is allowing the firmware to be loaded into the FPGA after choosing the ADS5481-85 device type, I hope?

    Regards,

    Richard P.

  • In reply to WhiteHorse:

    With no LEDs lit on the TSW1400 except the power LED it seems that the TWS1400 is the problem. We have checked the power rails on the TSW1400: 3V3, 1V8, 2V5, 0V9, 1V1, 1V5, 3V0 and they fine. The customer is using Windows 8 could this be the problem? What else would cause the FPGA not to configure?
  • Guru 65890 points

    In reply to WhiteHorse:

    John,

    We have not done much testing with HSDC Pro using Windows 8. Is there a way the customer could try a pc with Windows 7?

    Regards,

    Jim

  • In reply to jim s:

    We discussed using a PC with Windows 7. All of their computers have windows 8 so it will be difficult for them. Does the FPGA only program once HSDC Pro is running or should it program once power is applied? The TSW1400 this customer is using was used by another customer and I am trying to rule out a hardware failure.
  • Guru 65890 points

    John,

     The FPGA is programmed everytime power is applied and the GUI mentions "Downloading firmware, please wait". We have had some customers who had problems with Windows 8 and some that have not. There has only been a couple of cases that I can think of. I am guessing this is your problem.

    Regards,

    Jim 

  • In reply to jim s:

    Hi,

    Our software development team also tells me that we have seen the HSDCPro run on a few Windows8 systems but that it has not been checked out fully.  There may be corner cases that may turn out to have an issue.

    But again, may i ask that we get a screenshot of the HSDCPro when they get this error message?  We would want to see in the screenshot what the GUI thinks may be loaded for the firmware by looking at the lower right corner for the firmware name and the lower left corner for the firmware revision. 

    One more thing to try in the meantime - i told you earlier what the 'name' of the firmware is for this device selection - ADC_BYTE_WISE_1CH.  There is a drop-down menu item for Download Firmware.  If they choose this menu item and then choose the firmware name ADC_BYTE_WISE_1CH does the firmware then download correctly?  (meaning that the HSDPRo shows this firmware type in the lower right and the LEDs on the hardware light up finally?) 

    Regards,

    Richard P.

  • In reply to Richard Prentice:

    Sorry for the delay Richard.  

    Here are two screen shots.  Each with a different ADC.  I can say that the FPGA is not being configured because the LED is not on.  HSDCPro does communicate with the TSW1400.   I had the customer try to download ADC_BYTE_WISE__1CH, but LEDs on the hardware didn't light up.  Also, ADC_BYTE_WISE_1CH is not showing up in the lower right hand corner of HSDPro.  

    Customer has said that they only have Windows 8 available. 

    Regards,

    John Wiemeyer

  • In reply to WhiteHorse:

    The customer was able to locate a Windows 7 computer.  Now with Windows 7 they are still having the same problem.  Here are the screen shots.

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.