I am wondering if the internal clock dividers of the DAC5674 are cleared when the reset is pulsed. I will be operating the device in external 4x clock mode, and I need to guarantee a consistent phase relationship between the input clock (CLK/CLKC) and output clock (PLLLOCK) from reset-to-reset. I would assume that there is a fixed number of input clock cycles between the falling edge of the reset and the first rising edge of the output clock, but I want to make sure that is the case.
Thanks,
Mike
