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Will the ADS7883 work with a jittery clock? The only clock is SCLK which can be intermittent.
I'm assuming that only the falling edge of ~CS (Conversion Start) needs low jitter.
The ADS7883 will function provided that the SCLK timing requirements of page 4 are always met, (twH, twL, td1, td2, etc).
As you have mentioned, one source of noise when converting an AC signal is the jitter on CS, where the CS falling edge defines the sampling instant. However, this is a SAR ADC where SCLK is the conversion clock controlling the timing between binary bit decisions. The device is characterized with a low jitter SCLK clock and there is no data on the performance degradation that occurs on the ADS7883 with SCLK jitter.
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In reply to Luis Chioye:
In reply to David Wilens:
The noise degradation that occurs is primarily due to the aperture delay error; and this is a function of the CS jitter and the input frequency that is being sampled.
At the end of the acquisition time where the conversion period starts, the SAR ADC samples the reference voltage several times during each conversion (12 times in this case), where the reference circuit must remain stable during each sample. In addition, the internal comparator and CDAC must be settled, therefore, provided that the minimum twL, twH periods are met, I expect the ADC will function as expected, however, I currently have no data on the ADS7883 SCLK frequency jitter vs performance (if any occurs); and I would need to verify with design.
What is the max sampling rate required in the application? What is the max input frequency? What is the SCLK frequency and amount of jitter expected on SCLK?
It appears that 2% jitter will be allowed. I will need to consult with the designer on the reason Twh and Twl are a function of Tsclk (0.45xTsclk) instead of fixed time. Some other classical SAR ADC's define the jitter spec as a fixed value.
Confirmed with design: the ADS7883 will tolerate jitter on SCLK without degradation on performance provided that the timing specifications are met. The minimum hi and low SCLK pulse specifications are generally related to the digital interface to ensure pulses are properly detected. From the SAR ADC perspective, the internal CDAC and comparator will settle provided that the min SCLK period is met.
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