DAC38RF84: Serdes PLL calculation

Hi,
There are two PLLs and i was wondering how they are interconnected to each other ( before or after the Prescalar of the DAC PLL).
Si If i take the scematixc of GUI as reference, I will get a SERdes PLL REFCLK= DACClock/(prescalar*divider)=DACClock/12 with divider=3.
My interpolation is 12 which makes the Baseband Input rate to be the same frequency as SERDES PLL REFCLK. Is it issue please?

F,

Your equation is true if you are not using the DAC PLL. If you are using the DAC PLL, replace DACCLock with DAC PLL in your equation. Why is this a concern? Are you having issues with your setup? The PLL's are connected as shown in the GUI block diagram.

Regards,

Jim 

Hi Jim,
thank you for the previous answer.
I am just running a simulation with the GUI and not doing any test of hardware yet.
I am using the DAC PLL to get the SerDes PLL REFCLK through the predifined prescalar( 4) and divider(3).
I have a concern on the fact that the baseband input rate frequency has the same value that the SerDes PLL REFCLK frequency (interpolation of 12).
Any possibility to have an interference or timing issue between the two signals inside the chip that could affect the integrity of the data.
is it good practise?
Regards

F,
I would use the GUI in simulation mode to determine what these frequencies need to be. If you deviate from this, you could end up with timing issues.
Regards,
Jim