Hi,
It looks like there are 4 drive current levels for the SYNCb output, specified in Config52[15:14].
My question is, what are the semantics of Config52[15:14]?
Hopeful thanks --todd
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Hi,
It looks like there are 4 drive current levels for the SYNCb output, specified in Config52[15:14].
My question is, what are the semantics of Config52[15:14]?
Hopeful thanks --todd
Hello Todd,
These registers are meant to adjust the output current of the LVDS driver from 2mA to 4mA differential output. You can actually use our IBIS model to simulate the driver + PCB + your FPGA SYNC LVDS receiver altogether to see if any adjustment is needed for optimal loss profile + signal integrity.
Hello Todd,
We were able to measure the corresponding output voltage and current based on the settings. please see attached measurement results for reference. We also included the bias level in case you are interfacing with 0.9V based LVDS receiver.
SYNCB Characterization DAC38j84.xlsx
-Kang