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DAC3482:

Part Number: DAC3482
Other Parts Discussed in Thread: ADS4249

Hello,

In my application I sample 2 analog signals at 250 MHz. using ADS4249, transmit it and reconstruct it using DAC3482.

I noticed that DAC3482 has internal interpolation filters. Because of my sampling rate, I can use maximum X4 filter (DAC works up to 1.25 GHz) . I understand that those filters are for easy smoothing of the output Analog signal.

The question is whether those filters would remove any frequency higher than 125 MHz. which is sampled at the ADC stage?

What would happen if there is a 200 MHz. component in the Analog signal input? (i.e. ADC input). Would the interpolation filter remove this frequency? (because 200 MHz. is higher than 250 MHz. X 0.6 = 150 MHz.) or there would be folding (aliasing) and I will see a peak at 50 MHz. at the Analog output?

If I would see this peak, what is the way to filter it without losing my bandwidth? I need a bandwidth of DC-100 MHz.

Traditional anti aliasing filters (with linear phase) are -20, -40 or -60 dB's per decade so if I will make a 6'th order filter with -60 dB's per decade and a 100 MHz. Bandwidth (i.e. -3dB's at 100 MHz. = about -10 dB's at 200 MHz.) then I would still get aliasing. Higher order filters do not work at those frequencies because they accumulate DC offset error (and higher delays).

Is there any better way to do it without losing my DC-100 MHz. bandwidth and without the need to buy a much faster ADC and do digital filtering in the FPGA which samples (because it is expensive... Faster ADC and faster FPGA = more $$$).

I would appreciate your fast and detailed response.

  • Hello

    aronii said:
    The question is whether those filters would remove any frequency higher than 125 MHz. which is sampled at the ADC stage?

    With the ADC sampling at 250MSPS, anything higher than 125MHz (ADC Nyquist) would already be aliased back into baseband before the DAC inteprolation filter. The DAC will not be able to differentiate any of the aliased image within the ADC sampling.

    All the interpolation filter does is basically increase the "effective" DAC sampling rate and push out the DAC Nyquist zone. 

    To filter out the ADC input higher than 125MHz, you will need to look into some of our ADC parts with build in decimation filtering.

    aronii said:
    What would happen if there is a 200 MHz. component in the Analog signal input? (i.e. ADC input). Would the interpolation filter remove this frequency? (because 200 MHz. is higher than 250 MHz. X 0.6 = 150 MHz.) or there would be folding (aliasing) and I will see a peak at 50 MHz. at the Analog output?

    The DAC interpolation filter may not be able to properly filter out the image (from DAC aliasing at the baseband) due to the roll-off of the interpolation filter.

    aronii said:
    If I would see this peak, what is the way to filter it without losing my bandwidth? I need a bandwidth of DC-100 MHz.

    Best to use anti-aliasing filter at the ADC input, or pick ADCs with build in decimation filtering. Yes, some of our ADCs with build-in decimation may have higher cost, but it is the whole reason to more effective filtering since the digital filter can have much sharper roll-off than analog filters.

    Please check out the following tutorial regarding DAC interpolation

    -Kang

  • Thanks for your detailed response. I got 2 more questions:

    1. Can you offer an ADC with resolution of 14 bits or more with internal decimation filters? I need one with minimum sampling rate of 250 MHz., better with 2 channels.

    2. Is there any practical difference between a decimation filter inside the ADC to one inside the FPGA?

    Regards,

    Avi

  • Hi,
    1. I will have to refer you to our product selection page for more detailed selections based on your applications:
    www.ti.com/.../products.html
    2. not really. This is done at the cost of FPGA resource.

    -Kang