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ADS61B29: Questions about trace lengths and proper termination to FPGA

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Replies: 3

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Part Number: ADS61B29

Team,

I have a customer designing with ADS61B29, and they want to use the CLKOUT differential LVDS pair from the A/D as the main clock input clock for their FPGA (A/D is always on so no reason this CLK out couldn’t be the main board clock source) 

Is it recommended to use an external 100Ohm resistor with two inline 0.1uF capacitors decoupling the line as in the datasheet for this type of use case? 

If so, as a follow up, my understanding is that the trace length of all the LVDS pairs should be within 5mm of each other in overall length… the A/D data lines range in length from 14.1mm to 14.7mm in length, however the CLKOUT line was 19.1mm (due to the nature of where the CLK out pins are on the A/D in and where the PLL input lines are on the FPGA). Adding this resistor and capacitors will obviously shorten their trace length, but would they have to take the width of these components into account when adhering to this within 5mm spec, or do they ignore that and purely go with the trace length?

 

Best Regards,

Carolus Andrews, Analog Applications, Current and Hall Effect Sensors

Getting Started with Current Sensing Video Training Series

TI makes no warranties and assumes no liability for applications assistance or customer product design. You are fully responsible for all design decisions and engineering with regard to your products, including decisions relating to application of TI products. By providing technical information, TI does not intend to offer or provide engineering services or advice concerning your designs.

  • Hi Carolus,

    We are looking into this.

    Thanks,
    Eben.
  • In reply to Ebenezer Dwobeng:

    Ebenezer,

    Thanks for the response. The initial question was resolved via email, but I've had some followup questions come up as well:

    1. Is there an absolute maximum voltage for Vcm where potential damage to the device could occur?
    2. Is it possible to saturate on this ADC? If so, do we have any information regarding recovery?

     

    Best Regards,

    Carolus Andrews, Analog Applications, Current and Hall Effect Sensors

    Getting Started with Current Sensing Video Training Series

    TI makes no warranties and assumes no liability for applications assistance or customer product design. You are fully responsible for all design decisions and engineering with regard to your products, including decisions relating to application of TI products. By providing technical information, TI does not intend to offer or provide engineering services or advice concerning your designs.

  • In reply to Carolus Andrews:

    Hi Carolus,

    1. From datasheet Page 4, the volatge at the analog input pins should never go below -0.3V or above min(3.6V, AVDD+0.3)
    2. The ADC will saturate if you exceed the 2Vpp Full scale differential swing. The ADC will recover immediately when the input differential swing is restored to 2Vpp or under. However if the absolute max rating was violated, the operation of the ADC can not be guaranteed.

    Thanks,
    Eben.

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