Team,
I have a customer designing with ADS61B29, and they want to use the CLKOUT differential LVDS pair from the A/D as the main clock input clock for their FPGA (A/D is always on so no reason this CLK out couldn’t be the main board clock source)
Is it recommended to use an external 100Ohm resistor with two inline 0.1uF capacitors decoupling the line as in the datasheet for this type of use case?
If so, as a follow up, my understanding is that the trace length of all the LVDS pairs should be within 5mm of each other in overall length… the A/D data lines range in length from 14.1mm to 14.7mm in length, however the CLKOUT line was 19.1mm (due to the nature of where the CLK out pins are on the A/D in and where the PLL input lines are on the FPGA). Adding this resistor and capacitors will obviously shorten their trace length, but would they have to take the width of these components into account when adhering to this within 5mm spec, or do they ignore that and purely go with the trace length?
