ADS5272 range

How about the input clock? Is it called ADCLK in the datasheet?

Is the output clock for desrializer 12x of the input clock?

The input clock (the sample clock) is called ADCLK, while the output frame clock is an LVDS pair called ADCLKP/ADCLKN.

The frame clock (ADCLKP/ADCLKN) is at the same rate as the sample clock.  The bit clock that clocks the serialized LVDS data (LCLK) is at a rate 6x the input clock.  The rising and falling edges of the LCLK are to be used to latch the serial data into the FPGA or ASIC or whatever is to receive the serialized data.   Please see the LVDS timing diagram on page 8 of the datasheet.

Regards,

Richard P.

Thanks Richard. Got it!

I have an ADS5272EVM, and connected a 20MHz clock to the board. I can see a clock of 6x at LCLK. However, the amplitude seems to be very low (<0.9V).

I've applied an input DC signal, ranging from -1 to +1, to the channel 8. But I don't see any change at the serialized data at OUT8 based on the input changes. I can't see even a periodic signal (as the input is DC).

I'm not sure if I need to configure the board. 

Any help would be really appreciated.

Hassan

Hi,

The clock and serialized data outputs are LVDS, so they should be a low amplitude signal.  (about 350mV swing on each side of the signal for a peak to peak differential swing of about 700mV.  Centered at about 1.2V common mode.)

Our EVMs are generally configured with transformer coupled inputs, so a DC signal at the SMA of the EVM will not get through to the input pins of the data converter. The transformer coupling is an effective AC coupling, which could also be called a DC block.  Depending on the part number of the transformers used, an input signal of about 1MHz or higher should get through to the data converter, and the transformer coupling also converts the single ended input signal from the SMA to differential for the ADC.

You should not need to access the registers of the ADC to get basic operation from the EVM.  You may need to be sure to apply a reset by way of the reset switch.

Regards,

Richard P.

Thanks Richard.

I've connected a 20MHz clock with 1V to the board. the same signal is connected to the port 8, via an splitter. I expect to see a periodic signal at the serialized data, which goes to an FPGA board. but both the uncoded serial signal on an scope and the decoded data on the FPGA look like a random signal!!

do I have to buy the deserializing board (ADSDESER-50EVM) too? however, this module is not availabe by TI anymore. actually Iprefer to catch the serial data.

Hassan

Hi,

i would not expect to see a periodic signal on the serialized data, or even to recognize periodic patterns within the bit positions of the serialized data relative to the frame clock edges.  I think the data would need to be deserialized first. 

Deserializing the data on each channel *is* the function of the ADSDESER-50 EVM, and presenting the sample data on header posts to be captured by a logic analyzer or whatever you wish to use.  I will ask about the status of the ADSDESER-50, but I do think the stock on that has be running down.

We also make available a newer FPGA-based capture card to deserialize the data channels from our 1-wire and 2-wire serial devices - and that is the TSW1200,  However the connector used on the ADS5272 EVM predates the TSW1200 and they do *not* match up. We have recently fabricated an adapter board to let the ADS5272 EVM plug into the TSW1200 for deserialization *and* capture buffer and post-processing on a PC, but there remains a troubling detail that the ADS5272 serializes its data lsb-first and the TSW1200 expects to see the data serialized msb-first.  So the TSW1200 can capture the raw data and store it in a file name on a PC for something else to post-process - until such time as i can make the TSW1200 software accept either lsb-first or msb-first data.

if you already have the serial data going to an FPGA board, then you could deserialize the data in the FPGA the way the ADSDESER-50 does or the way the TSW1200 does.  Assuming you can catch the serial data bits correctly using the DDR bit clock - meeting setup and hold time into the FPGA - then deserializing the data bits back to sample data is not too hard.  I've attached a block diagram of how we do the job in the TSW1200.  The essence of the logic as that i run the data bits from the serial input through a chain of flip flops hooked up in a shift register format deep enough to at any one time hold the bits for a complete sample in the depth of the chain.  At the same time i am also latching in the frame clock as if it were another data channel.  But on the frame clock, i am looking for the clock cycle in which the frame clock is logic high while on the previous cycle it had been a logic low.  This will happen once per sample.  I make a single cycle 'load pulse' from this occurrence and use it to load the contents of the shift register chain into a parallel register.  Now i have a complete sample.  I may have to pad the depth of the shift register chain by one or two flops to account for the time it takes to detect frame clock going high and to create that load pulse - in order to make the 'sample' really contain the correct 12 bits of the sample data.

Regards,

Richard P.

Thanks Richard for the detailed explanation.

I have implemented the serial to parallel block on the FPGA and it works fine. my problem is with the connection of ADS5272EVM and the FPGA as the serialized data of ADS5272EVM is a differential pair. I have no idea how the ADS5272EVM generates the serialized bits into a "pair". but anyway they need to be subtracted since the FPGA only recognizes 0 and 1. I'm currently doing the subtraction in the first block of my FPGA circuit. the FPGA first converts the pair to binary format and then does the subtraction. my employed rule is:

OUT8P  OUT8N   Serialized output detected by FPGA

0               0                    0

0               1                    1

1               0                    1

1               1                    0

however, I think this causes some detection error as the subtraction should be done before the FPGA converts the signal to binary format. 

what do you think?

 Hassan

Hi,

The serialized data from the ADS5272 (as well as the bit clock and the frame clock) are all LVDS, which is a differential signalling standard.  On your FPGA you should be using LVDS input buffers, which accept the differential inputs and then provide a single ended logic signal for the internal logic of the FPGA.  There is no definition for the condition of OUT8P = 0 and OUT8N = 0 at the same time - this is not allowed.  An LVDS driver is (usually) a current mode driver in which for a logic '1' there is 3.5mA of current flowing out of the 'P' pin and into the 'N' pin.  And for the logic '0' state the current turns around and flows the other direction.  So if the differential pair is terminated into a 100 ohm resistor (required!) then there will either be a nominal +350mV voltage across the input differential pair or a -350mV voltage across the input pins.  One or the other, and one of these states is a logic '1' and the other is a logic '0'.   Usually in an FPGA there is also the option of having that 100 ohm termination resistor be implemented in the FPGA.  If not, then the 100 ohm termination resistor must be placed external to the LVDS inputs and right in front of the input pins.

Your FPGA should have options for LVDS inputs, which makes the use of the LVDS differential pairs simple and automatic, as long as the pin assignment of the signals into your FPGA assigns the two lines of the differential pair to input pins that make up an LVDS input pair for the FPGA.

Regards.

Richard P.

Hi,

I connected a resistor and saw some changes on the scope. unofrtunately the firmware of my FPGA board does not support LVDS I/O standard. I'm using Xilinx Virtex-II Pro. The documents say it does, but it doesn't due to sofware version incompatibility.

any suggestion?

Hassan

Hi,

I took a quick look at the Xilinx documentation for the Virtex II Pro and see that it is not recommended for new designs.  I also see that it does support LVDS IO at a rate of up to 840Mbps and supports on-chip termination.

You will need to make use of this capability if you are to interface to the serialized data from the ADS5272 or any other ADC with LVDS IO.

I don't know what version of Xilinx software you are using to design into the Virtex II, but i have the ISE version 12 software on my machine as well as an older copy of ISE version 9.2.  I opened one of my projects with the ISE version 9.2 and selected the Virtex II as the device.  You would need to work with Xilinx at this point to see how to make use of the LVDS IO capabilities.

Regards,

Richard P.