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DAC9881: Power-Supply Sequence

Expert 1295 points

Replies: 8

Views: 340

Part Number: DAC9881

Hello,

I understand that Power-Supply Sequence is AVDD ⇒ IOVDD,reference.

But my customer power on AVDD, IOVDD and reference at the same time,
and it is performed the hardware reset(17pin /RST) after that.
Are there any problems?

When powering on AVDD, IOVDD and reference at the same time,
is there a possibility that a device is damaged?


Best regards,
itabi

  • Itabi-san,

    I believe the reason behind the power-supply sequence comments in the datasheet are due to the AVDD supply being the input to the internal POR comparator. If IOVDD were to come up first, the digital interface would not yet have been initialized by the POR which could lead to device corruption. Similarly the VREF ESD structure on the positive side are connected to AVDD, so if VREF were applied before AVDD the ESD cell would be forward biased and conduct to AVDD, which either has the possibility of damaging the ESD cell or effectively back-powering AVDD which also could corrupt the POR sequence.

    If all of the supplies come up at the same time then I don't think there should be any problems or risk to damage.

    I think a good way to validate would be to request an oscilloscope capture of the supplies ramping from the customer. If there is something unexpected happening, we should be able to make some observation from this capture.

    Kevin Duke, MGTS
    ADC Product Marketing Engineer

  • In reply to Kevin Duke:

    Duke-san,

    Thank you for your reply.

    What is the meaning of "device corruption" ?
    Is it destruction of device?

    Or is it that it doesn't work right?

    Best regards,
    itabi
  • In reply to itabi:

    Itabi-san,

    Sorry for the ambiguity.

    Essentially the POR circuit is critical for triggering a read-sequence for internal memory which contains many important parameters for configuring the device at start-up. This can include, but is not limited to, trim coefficients, default register contents, and in some cases even the resolution settings for the device.

    In such a case, the device would not be permanently damaged - however it may exhibit some of these unexpected properties.

    Kevin Duke, MGTS
    ADC Product Marketing Engineer

  • In reply to Kevin Duke:

    Duke-san,

    Thank you for your detailed explanation.

    POR and hardware reset are same behavior, aren't they?

    Best regards,
    itabi

  • In reply to itabi:

    Itabi-san,

    Not necessarily. The precise functionality varies from device to device. Sometimes Engineers will refer to a HW or SW reset which performs the complete POR either directly as a POR or as a "deep reset". In many devices the HW/SW reset simply restore the internal registers to their default values, however will not trip the complete reload of the internal memory I mentioned in my last post.

    As it turns out, reviewing some of my notes, I believe for the DAC9881 the HW reset does trigger the full POR or "deep reset", but I will confirm.

    Kevin Duke, MGTS
    ADC Product Marketing Engineer

  • In reply to Kevin Duke:

    Itabi-san,

    I am close to having an answer to confirm this. Just need one more look with the design engineer.

    Kevin Duke, MGTS
    ADC Product Marketing Engineer

  • In reply to Kevin Duke:

    Itabi-san,

    I apologize for the delay. I ended up being quite sick for the last several days and had to take some personal time.

    I can confirm that the HW Reset will reload the OTP, however in order to ensure a complete and accurate latching of the OTP we recommend that the reset pulse width to be at least 1us.

    Kevin Duke, MGTS
    ADC Product Marketing Engineer

  • In reply to Kevin Duke:

    Duke-san,

    Thank you for your in-depth confirmation.
    We'll have the reset pulse width to be at least 1us.

    Best regards,
    itabi

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