ADC12J4000EVM: Timestamp jitter, rise and fall times

Yoni Sher

Part Number: ADC12J4000EVM

Hi,

The datasheet states (on page 44, section 7.3.7.2.11) that the timestamp is sample at "approximately" the same time as the signal. What does "approximately" mean? Is the timing between sampling the signal and the timestamp fixed? How far apart might the two be?

Additionally, what must the rise and fall times of the timestamp input be to be correctly recognized by the module?

Thanks,

Yoni

over 5 years ago

0 Jim Brinkhurst1 over 5 years ago

TI__Mastermind 43940 points

Hi Yoni
I'm checking to see if there is any simulation or measurement information regarding the aperture delay time for the timestamp input as compared to the aperture delay for the analog inputs.
The rise and fall times of the signal are not critical for basic capture of timestamp. To get the most accurate time resolution on timestamp the rise/fall times should be less than the sample period. For a 4 GHz input clock the ADC sample period is 250 ps, so ideally the timestamp signal would have a rise and fall time lower than 250 ps.
Best regards,
Jim B

0 Jim Brinkhurst1 over 5 years ago in reply to Jim Brinkhurst1

TI__Mastermind 43940 points

Hi Yoni
I have not located any simulation or measurement data for the timestamp input aperture delay. The only information I have found is the description in the datasheet stating that timestamp is sampled at approximately the same time as the analog input.
Best regards,
Jim B

0 Yoni Sher over 5 years ago in reply to Jim Brinkhurst1

Prodigy 150 points

Hi Jim,

At the very least, once I have done my experiment, can I send you the data so that you will have a better answer for the next people to ask?

Yoni

0 Jim Brinkhurst1 over 5 years ago in reply to Yoni Sher

TI__Mastermind 43940 points

Hi Yoni
Yes if you want please share your results once you have the data.
Best regards,
Jim B

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ADC12J4000EVM: Timestamp jitter, rise and fall times