• State TI Thinks Resolved
  • Locked Locked
  • Replies 3 replies
  • Answers 1 answer
  • Subscribers 46 subscribers
  • Views 473 views
  • Users 0 members are here
Support feedback
Options
Options
Similar topics

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

ADS1255: DOUT is not output issue

Tsukui Yusuke
Guru 21930 points
Part Number: ADS1255

Hi,

Customer is troubled because DOUT is not output.
Please tell me about the following two questions.

1.Could you tell me the concept of T1 max.
   The following contents are described in the data sheet.
   I understood the meaning of T1 min.
   However, I can not understand T1 max.
   What does Tdata specify in the timing chart?

   "τDATA = output data period 1/fDATA"




2. Should CS pin be low each time data is acquired?
    Is it possible to use it with Low fixed?


Regards,
Yusuke

  • 0
    TI__Mastermind 44550 points
    Hi Yusuke-san,

    I can help answer your questions...


    1) T1 is specifying a minimum SCLK frequency, below which the SPI communication will not work.

    ...I am unsure of why the minimum is "10 / tDATA" (1 clock period every 10 conversion periods). The SPI interface will timeout if SCLK is held low for 32 conversion periods, not 10, hence this seems somewhat arbitrary to me. I will let you know if I can find more information on why this is the case. However, I would recommend that SCLK not be any slower than about (1/32) / tDATA (i.e. at least 32 SCLK periods within a conversion period), and preferably even faster than that. If the SCLK frequency is so slow that it is not capable of issuing an "RDATA" command and clock out 24-bits of data, then it will be too slow to capture every conversion result. While the SPI communication may be function, it is not practical.

    Please do recommend to your customer that they try to keep SCLK fast enough to ensure that there is plenty of time to read the ADC data, well before the next /DRDY falling edge occurs!


    2) Yes, /CS must be low to communicate with the device. Either it can be toggled low or fixed low.

    I would highly recommend toggling /CS if given the option. Toggling /CS resets the SPI and allows for communication to begin from a known state. Holding /CS low makes the SPI communication susceptible to noise on the SCLK signal. If the slave device sees an extra SCLK pulse (due to noise) then it may clock out an extra bit and get 1 clock period ahead of the SPI master device. The only way to recover from such an error would be to hold /CS low for 32 conversion periods (the SCLK timeout period) or to reset the device.



    If you customer is not seeing a DOUT signal, then I would first recommend checking if there is a /DRDY output. "/DRDY" can act as a "heartbeat" to let you know if the ADC is powered and actively converting. It is typically present if 1) the ADC is fully powered, 2) the ADC has a clock signal, and 3) the GPIO pins are sent correctly to allow the device to run (i.e. not held in reset, sleep, or a power down state). Check for /DRDY first and let me know if there are still issues with the DOUT signal.
  • 0 in reply to Christopher Hall
    Guru 21930 points

    Chris-san,

    Thank you for your kind support.
    Customer did not mistake the clock timing rules.
    The problem was solved by reviewing the GND layout.

    There's one more thing I'd like to ask you about.

    1.This device issues an AD data fetching command immediately after the DRDY signal goes low.
       Is the same time "DRDY Low" to issue all other commands?

    2.It seems that 24bit AD data is acquired after the DRDY signal goes low.
       However,If the acquisition clock speed is slow, the DRDY signal goes low again during AD data acquisition.
       In this case, 16 bits are sufficient. Is there a problem with how to use only 16 bits and exit?

    Regards,
    Yusuke

  • 0 in reply to Tsukui Yusuke
    TI__Mastermind 44550 points

    Hi Yusuke-san,

    1) I didn't fully understand your first question...

    • All commands require a small delay from when /CS goes low to the first SCLK (t3), if the /CS pin is used.
    • Some commands (RDATA, RDATAC, and RREG) require a small delay between issuing the command on DIN and seeing the response on DOUT (t6).
    • Some commands require waiting for /DRDY to go low before issuing another command, see the full list on pg6 of the datasheet.
       

    2) You can decide to stop reading data after clocking out 16-bits, but only if you are controlling /CS. If /CS is tied low, then you'll need to read out all 24 bits.

    If possible try to avoid using too slow of an SCLK that is not fast enough to clock out all of the data before the next /DRDY falling edge, or reduce the ADC's data rate to allow more time to clock out the data.