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Part Number: ADS1255
Hi,Customer is troubled because DOUT is not output.Please tell me about the following two questions.1.Could you tell me the concept of T1 max. The following contents are described in the data sheet. I understood the meaning of T1 min. However, I can not understand T1 max. What does Tdata specify in the timing chart? "τDATA = output data period 1/fDATA"2. Should CS pin be low each time data is acquired? Is it possible to use it with Low fixed?
Best regards,Chris HallApplications Engineer | Precision ADCs
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In reply to Christopher Hall:
Chris-san,Thank you for your kind support.Customer did not mistake the clock timing rules.The problem was solved by reviewing the GND layout.There's one more thing I'd like to ask you about.
1.This device issues an AD data fetching command immediately after the DRDY signal goes low. Is the same time "DRDY Low" to issue all other commands?2.It seems that 24bit AD data is acquired after the DRDY signal goes low. However,If the acquisition clock speed is slow, the DRDY signal goes low again during AD data acquisition. In this case, 16 bits are sufficient. Is there a problem with how to use only 16 bits and exit?Regards,Yusuke
In reply to Tsukui Yusuke:
1) I didn't fully understand your first question...
2) You can decide to stop reading data after clocking out 16-bits, but only if you are controlling /CS. If /CS is tied low, then you'll need to read out all 24 bits.
If possible try to avoid using too slow of an SCLK that is not fast enough to clock out all of the data before the next /DRDY falling edge, or reduce the ADC's data rate to allow more time to clock out the data.
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