Hello team,
my customer is trying to understand the "optional clock stretching" mechanism in the ads7142-q1.
they have a Master I2C in the form of CPLD and we are writing the VHDL code to manage the A2D,
it appears that the clock Stretching is optional as mention in the datasheet,
but they are trying to understand if they can work with the A2D without clock stretching?
do they need to configure it to this mode and how?
they plan is to work in manual mode, please advise?
Best regards,
Shai