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ADS7142-Q1: clock stretching

Part Number: ADS7142-Q1

Hello team,

my customer is trying to understand the "optional clock stretching" mechanism in the ads7142-q1.
they have a Master I2C in the form of CPLD and we are writing the VHDL code to manage the A2D,
it appears that the clock Stretching is optional as mention in the datasheet,
but they are trying to understand if they can work with the A2D without clock stretching?
do they need to configure it to this mode and how?
they plan is to work in manual mode, please advise?

Best regards,

Shai

  • Hi team,

    Could you please advise, Thanks.

    Shai

  • Hello,

    The device is by default not doing clock stretching.

    This feature will automatically turn on if the device needs to.

    Clock stretching will happen automatically if the slave cannot support the clock/bus speed (for example the slave data is not ready) and the slave will hold the clock low until it is ready to resume.

    What rate do you plan to run the device? be sure to have Tsclk low time greater than 1.8us to avoid clock stretching.

    It is likely the your CPLD cannot support this.

    Regards

    Cynthia

  • Hi Cynthia,

    We are trying to understand if in our specific mode of operation the CLK stretch will not activate.

    this means working in manual mode and reading the value of the A2D (only one channel connected) by demand,

    or is there a frequency or a mode of operation they can recommend that ensures that there will be no CLK stretching

    Could you please verify if we plan to work in 100KHz SCL, that means every cycle is 10usec and Tscl-low is 5usec>1.8usec

    that means there will not be any clock stretch in a manual mode according to this :

      

    A fast response time will highly be appreciated it is critical for our design and needs to be solved fast.

    Many thanks.

    Best regards,

    Shai

  • Hello,

    You should not experience clock stretching given the information you provided.

  • , Thank you very much.

    regards,

    Shai