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ADS5294: ADS5294

Alan Dent
Prodigy 30 points
Part Number: ADS5294

I wish to use this part with a burst sample clock. Two questions.

1) Are there any issues with the timing for the first few samples.

2) Do extra clocks have to be supplied to flush the pipeline at the end of the burst or will it flush automatically.

The sample clock will be bursts of 20MHz ranging from a few hundred clocks up to 17k clock at rates of a few Hertz to a few hundred Hertz.

Many Thanks.

Alan

  • 0
    TI__Expert 6040 points

    Thanks for looking at our part!

    if ADC CLK is burst, we have to rerun the LVDS timing caliabration and initialziaiton. Device's internal PLL needs time to settle as well. Thus we have to treat each burst cycle as a seperate power up/down sequence. 

    since your repition freq is Hz, you have sufficent time to run synchronized the clock and realign LVDS timing. you can refer to datasheet's power up timing, there we put 1ms as the reset timing. So ADC clock has to be applied for 1ms to ensure ADC data is valid.  hope 1~2ms reset timing would be good for you. 

    another way is to put ADC into the paritial power down mode, but keep ADC CLK running. this way, LVDS link is always active and you can return to data capture in 5~10us . of cousre, partial power down power consumpiton is slightly higher. 

    Thanks!

  • 0 in reply to Xiaochen (Sean)Xu
    Prodigy 30 points

    Many thanks for your answer. I can provide the necessary run up for the PLL.

    However, your answer has raised a further questions.

    1) If I do not provide the run up,  would the input clock - sample time remain stable.

    2) If I do not provide the run up, does the LVDS Bit Clock, Data & Frame Clock timing remain stable relative to each other. I can tolerate them moving around as a block, but obviously not moving relative to each other.

    3) With a burst clock, when it ends do I have to provide the extra clocks to flush the pipeline or will the PLL continue to run and flush the pipeline automatically, albeit with potentially slightly different timing.

    Thanks Again.

  • 0 in reply to Alan Dent
    TI__Expert 6040 points

    1. Typically we require 100us to keep ADC clock stable for data output. So a run up of >100us is must before capturing the data. 

    2. the 100us also applies to the LVDS bit clock FCLK etc, which are coming from the PLL block. when the PLL is not reaching the lock state, the relationship between data, FCLK/BCLK are undertmined. 

    3. ADC has a latency of 11 to 15 cycles, thus you have to make sure ADC clock running for at least that many cycles in order to flush sampled ADC data out. our chip won't automatically flush ADC output. 

    Thanks!

  • 0 in reply to Xiaochen (Sean)Xu
    Prodigy 30 points

    Thank you for your help. I now have enough information for me to decide how to proceed to use the device.

    Thanks again.