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ADS8325: DOUT remains low after CS asserted

Shota Mago
Expert 6580 points
Part Number: ADS8325
Other Parts Discussed in Thread: ADS8353

Hi team,

My customer considers to use ADS8325IB and provided some questions.

  1. DOUT becomes low after power up and it keeps low even after CS asserted.
    Is there possibility that ADS8325 broken?
  2. Timing Chart shows that max TCSD is 0ns.
    Does it mean DCLOCK needs to be low before CS becomes low?
    If this timing is violated, will communication error occur?

Best regards,

Shota Mago

  • 0
    TI__Guru 57346 points

    Hello Shota-san,

    Thank you for your post.

    Can you please clarify which part number you are referring to?

    Best regards,

  • 0 in reply to Ryan Andrews
    TI__Expert 6580 points

    Hi Ryan-san

    Sorry for my typo.

    I meant ADS8325IB. ADS8353 has nothing to do with it.

    Best regards,

    Shota Mago

  • 0 in reply to Shota Mago
    TI__Mastermind 24940 points

    Hello,

    1. the SDO is High Z, which means it will remain in the state it last was when not controlled. Note also that the first 5 SCLK are not valid SDO data and that the pin is still High Z

    To understand, do you mean that the device does not output any data when converting?

    Can you use a known DC input, and sample out the data, this way we can compare what the output is expected to be vs what it is. Also make sure there is nothing on the digital line that could be holding the signal.

    2. the SCLK does not need to be low before CS, but it would need fall with CS falling.

    A screen shot of the digital lines will help to debug and confirm timing.

    Regards

    Cynthia

  • 0 in reply to Cynthia
    TI__Expert 6580 points

    Hi Cynthia-san

    Thank you for your reply.

    1. The device looks output data successfully but the customer just would like to know idle state of DOUT.
        I understood that DOUT will remain in the state of previous one thanks to your answer.
        What about DOUT status at start-up? (default low?)

    3. Should the customer set SPI mode 1 for the device?

    Best regards,

    Shota Mago

  • 0 in reply to Shota Mago
    TI__Mastermind 24940 points

    Hello,

    there is not information on what the default level of SDO when device is initially powered up, but notice that SDO will go low for a clock cycle before the MSB is clocked out at every conversion result.

    From the timing diagram below, the data should be read on the rising edge of SCLK, 

    SPI mode 1 has data read on the falling edge, thus this would not be a good choice. I would suggest mode 0

    Regards

    Cynthia