Part Number: DAC81408
I have a design that uses the first 4 channels as arbitrary waveform generators running at a 400Khz update rate (at 50Mhz SPI) and then synchronously updating them. The four remaining DACs are used as utility DACs that can be updated at any time. My RTL design uses the streaming mode for the first 4 channels then tacks the channel update for one of the 4 utility dacks after the streaming of the first 4 DACs. However, after streaming DACS 1-4, then issuing an LDACn strobe, I run into issues if the next DAC is DAC5. the other 3 work fine. Is there a timing relation sip between the LDACn and selecting the next sequential DAC after the streaming selection?
Again, my sequence is:
1) CS low
2) 72 bits transferred - DAC1_ADDR (8bits), DAC1_DATA(16bits), DAC3_DATA(16bits), DAC3_DATA(16bits), DAC4_DATA(16bits)
3) CS high
4) 20nS delay
5) LDACn Strobe for 20nS
6) 15nS delay
7) CSn low
My colleague Uttam will respond to you when he is back in the office on Monday.
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In reply to Paul_Frost:
Excellent, I am running into all kinds of timing-related issues with the DAC81408 due to undocumented timing requirements. I know have the design mostly working accept that DAC1 only updates one out of 20-30 times writing to it but the remaining three in the stream mode work fine. There is some relationship not in the datasheet. Again, In my application, I need to update 4 DACs at a 400khz update rate and then one of the following of DAC 5-8 so I have 5 DAC updates per every 2.5uS. I think my issues are around the Toggle register B to Toggle register A timings but the datasheet mentions nothing about their relationship. In my design, the laser ARB waveforms cannot be interrupted.
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