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ADS8363: ADS8363 CONVST has a 16bit clock output

jianli wang
Prodigy 20 points
Part Number: ADS8363

I'm using the ads8363 chip right now..The acquisition of 4 channels is differential signal.When I write in the configuration register, the data is 0x1062 0x03fff 0x1065 0x03fff.CONVST this pin has an output of clock.I really don't understand why.Did I restore the chip to factory Settings? Or is the chip broken?

  • 0
    TI__Guru 60866 points

    Hello Jianli,

    Thank you for your post and welcome to our forum!

    The CONVST pin is a digital input, not an output. This signal must be controlled by your MCU to set the desired conversion cycle period.

    What is the status of pins M0 and M1?

    The sequence of commands look correct in order to write to the REFDAC1 and REFDAC2 control registers. Have you tried reading these registers before programming them?

    If you refer to Figure 37 in the datasheet, you will see that each register write requires two frames. In the first frame, you will send a pulse on CONVST/RD, followed by 0x1062 + 0h. Then, in the second frame, you will send another CONVST/RD pulse, followed by 0x03FF + 0h. (The " + 0h" is to complete the required 20 clocks per frame requirement).

    Best regards,

  • 0 in reply to Ryan Andrews
    Prodigy 20 points

    Well ,thank you for your reply!

    The M0 and M1 are both “0”. I selected the mode I.

    I have changed the phase between the SDI and CLOCK ,and I got the signal of SDOA and SDOB . I also changed the conversation channels from CHx_0 to CHx_3, but in my MCU I couldn’t get the right sequence(CHx_0 followed by CHx_3)  from SPI. Sometimes CHx_0 followed by CHx_3 and sometimes CHx_3 followed by CHx_0.

    Expecting your reply sincerely!

  • 0 in reply to jianli wang
    TI__Guru 60866 points

    Hello Jianli,

    Is your original issue resolved? Can you enable the internal reference voltage? This can be verified by probing the REFIOx output pins and measuring the voltage with respect to GND.

    Please see Figure 31 in the datasheet. There is a delay of two 20-clock frames between changing the input MUX and receiving the new conversion result. For example, if you change the MUX in the first frame, the A-to-D conversion will occur in the second frame, and the 16-bit results will be available to read in the third frame.

    Best regards,