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DAC11001A: What is the update rate with de-glitcher enabled?

Justin Scott
Intellectual 545 points
Part Number: DAC11001A

It is not clear to me from the datasheet what the update rate and settling time are when you have the de-glitch feature enabled. Please advise. Thanks!

  • 0
    TI__Mastermind 46290 points

    Justin,

    The team that supports this device is based in India, so there will be a bit of a delay for getting an update on this. Uttam, who I see you are already in communication with on another thread, will support you during his work day tomorrow. He should also have an update for you on the other topic.

  • 0 in reply to Justin Scott
    Prodigy 60 points

    Hi Uttam (when you get to this thread),

    I am Justin's colleague, and am trying to control the DAC11001A through the evaluation board using an external FPGA board.  I have been able to create a ramp waveform at the DAC output, but I am seeing voltage steps that indicate a 500 kHz update rate, even when I am sending updates over the SPI interface at 1 MHz.  I have tried changing the DIS_TNH and UP_RATE bits in the CONFIG2 register but haven't found a combination that gets the DAC to actually update at 1 MHz.  Do you have any insights into this behavior?

    Thanks,

    Jonny

  • 0 in reply to Jonny Ai
    TI__Genius 14220 points

    Hi Jonny,

    You should set DIS_TNH as 0 and UP_RATE as 000. Are you finding any issue there? Could you please upload the waveform you are capturing?

    Regards,

    Uttam

  • 0 in reply to Uttam Sahu
    Prodigy 60 points

    Hi Uttam,

    DIS_TNH=0 and UP_RATE=000 was the first combination that I tried.  My ramp waveform is below.  The datasheet mentions that setting DIS_TNH=0 limits the max update rate, but isn't very specific.  What exactly do the UP_RATE bits control within the device?

    -Jonny

  • 0 in reply to Jonny Ai
    TI__Genius 14220 points

    Hi Jonny,

    We have tested 1MHz update rate on the EVM in our lab and tested THD with that as well. Do you have the waveform with the 1MHz update rate? Are you finding it distorted? 

    Regards,

    Uttam

  • 0 in reply to Uttam Sahu
    Prodigy 60 points

    Hi Uttam,

    Here is a scope trace of the DAC output (pink) along with my LDAC_n (blue) and MOSI (green) signal:

    You can see that LDAC_n is strobing every 1 us while the DAC output is only changing every 2 us.

    I am controlling the DAC over SPI from a Xilinx FPGA.  Here is a capture of the logic in my FPGA, where each data point represents the value of a signal at the rising edge of a 100MHz clock.  If you are familiar with AXI-stream signalling, my DAC interface is accepting a new sample every 100 clocks (1 us), and I am not repeating the same value for 2 consecutive samples.

    -Jonny

  • 0 in reply to Jonny Ai
    TI__Genius 14220 points

    Hi Jonny,

    I suspect that somewhere there might be some tolerance with the 1MHz timing and the internal TnH hold time due to which the DAC is skipping alternate updates. You can try the next setting for UP_RATE, which is "011". We had tested the 1MHz update rate with this settling in our lab. Hence, this should work.

    Please expect some delay in the response due to the year-end vacations.

    Regards,

    Uttam

  • 0 in reply to Uttam Sahu
    Prodigy 60 points

    Hey Uttam,

    With some digging I discovered that my initialization procedure from the FPGA was not actually successfully writing to the CONFIG registers by performing a read back.  This appears to be because I did not wait long enough after performing a software reset.  When I removed the software reset from my initialization, the configuration registers were set correctly, and I was then able to see updates at 1 MHz.

    I arbitrarily waited ~40 us after the software reset before attempting to write to the configuration registers, since I did not see this time specified in the datasheet.  Do you have a more definitive number for this?

    Thanks,

    Jonny

  • 0 in reply to Jonny Ai
    TI__Genius 14220 points

    Hi Jonny,

    There is usually a time gap required between the reset and the start of programming. I will check with the team. Please expect some delay in my response unless someone from my team is able to take it up.

    Regards,

    Uttam

  • 0 in reply to Uttam Sahu
    Intellectual 545 points

    In regards to my original question, are there specs for the update rate and settling time with the de-glitcher enabled?