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Part Number: DAC3283
You will need to contact Abaco for additional support for the different modes of setting and the co-support package with Xilinx based FPGA. I (TI) am not familiar on how the Xilinx based FPGA support package are suppose to work under different modes
There are a couple of fundamental issues:
1. DATACLK should come from the FPGA as the DATACLK should be source synchronous and aligned with the DDR data. The DAC3283 has specific setup/hold time under the DAC3283 datasheet in the data bus specification. Please make sure that this is followed.
DAC3283 setup-hold definiton.ppt
2. the first mode has 1x interpolation, while the 2nd mode has 4x interpolation. The DAC sample rate is 16.384MSPS for both cases.
The data rate for 1x interpolation is 16.384MSPS. With 8 bit wide bus interleaved DDR, the DATACLK should be 2x 16.384MHz
The data rate for 4x interpolation 16.384MSPS/4. With 8 bit wide bus interleaved DDR, the dataclk should be 1/2*16.384MHz.
Basically, your dataclk rate for both cases are set incorrectly.
See below powerpoints for details on the setup
7128.DAC3282-3 Byte Wide DDR Clocking.pdf
Usually when FIFO has issue, it is due to the wrong clock rate or frame/ostr rate. You will need to double check the correct rate for each setting. For detail, you may refer to this application note.
There are existing firmwares of Xilinx based FPGA design that works with the DAC3283/ADS62p49 through the Avnet Speedway Design course. However, the firmware are owned by Avnet so you will need to contact them for additional support. TI cannot support firmware development.
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