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DAC3283: DAC configuration registers' setting issues

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Replies: 1

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Part Number: DAC3283

About using the Abaco FMC151 daughter board, I find some strange thing when I do the DAC (DAC3283) configuration registers' setting. I do the settings as follows. And I find the test results are not as my expection. I have no ideas about these test results. Could you kindly tell me what's wrong about these test results? Thanks a lot.
DATACLK: 16.384 MHz from CDCE72010.
DACCLK: 16.384 MHz from CDCE72010.
Sine wave pattern from FPGA: 1.024 MHz digital Sine wave pattern for 16-bit I-data and zeros for 16-bit Q-data.
                                                  Generate the DDR Byte-Wide Data Transmission Format by the Xilinx FPGA implementation.
Setting one: fir0, fir1 disabled with FIFO mode disabled
CONFIG0 Bit 6 (fifo_ena): 0 (FIFO mode disabled); Bit 5 (fifo_reset_ena): 1; Bit 4 (multi_sync_ena): 1 ; Bit [1:0] (mixer_func): 0x0
CONFIG1 Bit 5 (fir0_ena): 0; Bit 4 (fir1_ena): 0 (fir0, fir1 disabled)
CONFIG19 Bit 1 (multi_sync_sel): 1
Under Setting one, I find that the DAC output is with 8 levels per Sine wave cycle (I think that it's ok because the sampling clock rate for 16-bit I-data is 16.384/2 (= 8.192 MHz) and
                               the digital Sine wave pattern is with frequency, 1.024 MHz and the samples per digital Sine wave pattern's cycle should be 8 (8 = 8.192/1.024).
                               8 samples per digital Sine wave pattern's cycle is exactly the same as 8 levels per Analog Sine wave cycle and I think this is ok. ).
Setting two: fir0, fir1 enabled (x4 interpolation) with FIFO mode enabled (Changing the DACCLK from 16.384 MHz to 40.96 MHz)
CONFIG0 Bit 6 (fifo_ena): 1 (FIFO mode enabled); Bit 5 (fifo_reset_ena): 1; Bit 4 (multi_sync_ena): 1 ; Bit [1:0] (mixer_func): 0x0
CONFIG1 Bit 5 (fir0_ena): 1; Bit 4 (fir1_ena): 1 (fir0, fir1 enabled (x4 interpolation))
CONFIG19 Bit 1 (multi_sync_sel): 1 (Single Sync Source mode with FRAME controlled signal from Xilinx FPGA implementation)
Test results: No DAC output.
Q1: I have no ideas about why FIFO mode not work under this setting. Could you tell me what's wrong about this setting?
Setting three: fir0, fir1 enabled (x4 interpolation) with FIFO mode enabled (Keeping the DACCLK as 16.384 MHz)
CONFIG0 Bit 6 (fifo_ena): 1 (FIFO mode enabled); Bit 5 (fifo_reset_ena): 1; Bit 4 (multi_sync_ena): 1 ; Bit [1:0] (mixer_func): 0x0
CONFIG1 Bit 5 (fir0_ena): 1; Bit 4 (fir1_ena): 1 (fir0, fir1 enabled (x4 interpolation))
CONFIG19 Bit 1 (multi_sync_sel): 1 (Single Sync Source mode with FRAME controlled signal from Xilinx FPGA implementation)
Test results: Not Sine wave output.
Q2: I have no ideas about why FIFO mode doesn't output the x4 interpolation Sine wave under this setting. Could you tell me what's wrong about this setting?
Setting four: fir0, fir1 enabled (x4 interpolation) with FIFO mode disabled (Keeping the DACCLK as 16.384 MHz)
CONFIG0 Bit 6 (fifo_ena): 0 (FIFO mode disabled); Bit 5 (fifo_reset_ena): 1; Bit 4 (multi_sync_ena): 1 ; Bit [1:0] (mixer_func): 0x0
CONFIG1 Bit 5 (fir0_ena): 1; Bit 4 (fir1_ena): 1 (fir0, fir1 enabled (x4 interpolation))
CONFIG19 Bit 1 (multi_sync_sel): 1
Test results: Sine wave output with wrong interpolation (not x4, seems x2) test results.
Q3: Under Setting four, I find that the DAC output is with 16 levels per Sine wave cycle (I think that it's wrong because the sampling clock rate for 16-bit I-data is 16.384/2 (= 8.192 MHz) and
                                      the digital Sine wave pattern is with frequency, 1.024 MHz and the samples per digital Sine wave pattern's cycle after interpolation should be 32 (32 = (8.192/1.024)x                 
                                      4(interpolation)).
                                      32 samples per digital Sine wave pattern's cycle after x4 (interpolation) is not the same as 16 levels per Analog Sine wave cycle and I think this is wrong (It seems x2
                                      (interpolation) setting). ).
       Could you tell me what's wrong about this setting?
Setting five: fir0 enabled, fir1 disabled (x2 interpolation) with FIFO mode disabled (Keeping the DACCLK as 16.384 MHz)
CONFIG0 Bit 6 (fifo_ena): 0 (FIFO mode disabled); Bit 5 (fifo_reset_ena): 1; Bit 4 (multi_sync_ena): 1 ; Bit [1:0] (mixer_func): 0x0
CONFIG1 Bit 5 (fir0_ena): 1; Bit 4 (fir1_ena): 0 (fir0 enabled, fir1 disabled (x2 interpolation))
CONFIG19 Bit 1 (multi_sync_sel): 1
Test results: No DAC output.
Q4: I have no ideas about why Bypass mode not work under this setting. Could you tell me what's wrong about this setting?
Setting six: fir0 disabled, fir1 enabled (x2 interpolation) with FIFO mode disabled (Keeping the DACCLK as 16.384 MHz)
CONFIG0 Bit 6 (fifo_ena): 0 (FIFO mode disabled); Bit 5 (fifo_reset_ena): 1; Bit 4 (multi_sync_ena): 1 ; Bit [1:0] (mixer_func): 0x0
CONFIG1 Bit 5 (fir0_ena): 0; Bit 4 (fir1_ena): 1 (fir0 disabled, fir1 enabled (x2 interpolation))
CONFIG19 Bit 1 (multi_sync_sel): 1
Test results: Not Sine wave output.
Q5: I have no ideas about why Bypass mode doesn't output the x2 interpolation Sine wave under this setting. Could you tell me what's wrong about this setting?
Best Regards,
Eric Tsai
  • Hi Eric,

    You will need to contact Abaco for additional support for the different modes of setting and the co-support package with Xilinx based FPGA. I (TI) am not familiar on how the Xilinx based FPGA support package are suppose to work under different modes

    There are a couple of fundamental issues:

    1. DATACLK should come from the FPGA as the DATACLK should be source synchronous and aligned with the DDR data. The DAC3283 has specific setup/hold time under the DAC3283 datasheet in the data bus specification. Please make sure that this is followed. 

    DAC3283 setup-hold definiton.ppt

    2. the first mode has 1x interpolation, while the 2nd mode has 4x interpolation. The DAC sample rate is 16.384MSPS for both cases. 

    The data rate for 1x interpolation is 16.384MSPS. With 8 bit wide bus interleaved DDR, the DATACLK should be 2x 16.384MHz

    The data rate for 4x interpolation 16.384MSPS/4. With 8 bit wide bus interleaved DDR, the dataclk should be 1/2*16.384MHz. 

    Basically, your dataclk rate for both cases are set incorrectly. 

    See below powerpoints for details on the setup

    7128.DAC3282-3 Byte Wide DDR Clocking.pdf

    Usually when FIFO has issue, it is due to the wrong clock rate or frame/ostr rate. You will need to double check the correct rate for each setting. For detail, you may refer to this application note.

    http://www.ti.com/lit/an/slaa584/slaa584.pdf

    There are existing firmwares of Xilinx based FPGA design that works with the DAC3283/ADS62p49 through the Avnet Speedway Design course. However, the firmware are owned by Avnet so you will need to contact them for additional support. TI cannot support firmware development. 

    -Kang

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