Other Parts Discussed in Thread: CDCE72010, ADS62P49
DATACLK: 16.384 MHz from CDCE72010.
DACCLK: 16.384 MHz from CDCE72010.
Sine wave pattern from FPGA: 1.024 MHz digital Sine wave pattern for 16-bit I-data and zeros for 16-bit Q-data.
Generate the DDR Byte-Wide Data Transmission Format by the Xilinx FPGA implementation.
CONFIG0 Bit 6 (fifo_ena): 0 (FIFO mode disabled); Bit 5 (fifo_reset_ena): 1; Bit 4 (multi_sync_ena): 1 ; Bit [1:0] (mixer_func): 0x0
CONFIG1 Bit 5 (fir0_ena): 0; Bit 4 (fir1_ena): 0 (fir0, fir1 disabled)
CONFIG19 Bit 1 (multi_sync_sel): 1
Under Setting one, I find that the DAC output is with 8 levels per Sine wave cycle (I think that it's ok because the sampling clock rate for 16-bit I-data is 16.384/2 (= 8.192 MHz) and
the digital Sine wave pattern is with frequency, 1.024 MHz and the samples per digital Sine wave pattern's cycle should be 8 (8 = 8.192/1.024).
8 samples per digital Sine wave pattern's cycle is exactly the same as 8 levels per Analog Sine wave cycle and I think this is ok. ).
CONFIG0 Bit 6 (fifo_ena): 1 (FIFO mode enabled); Bit 5 (fifo_reset_ena): 1; Bit 4 (multi_sync_ena): 1 ; Bit [1:0] (mixer_func): 0x0
CONFIG1 Bit 5 (fir0_ena): 1; Bit 4 (fir1_ena): 1 (fir0, fir1 enabled (x4 interpolation))
CONFIG19 Bit 1 (multi_sync_sel): 1 (Single Sync Source mode with FRAME controlled signal from Xilinx FPGA implementation)
Test results: No DAC output.
Q1: I have no ideas about why FIFO mode not work under this setting. Could you tell me what's wrong about this setting?
CONFIG0 Bit 6 (fifo_ena): 1 (FIFO mode enabled); Bit 5 (fifo_reset_ena): 1; Bit 4 (multi_sync_ena): 1 ; Bit [1:0] (mixer_func): 0x0
CONFIG1 Bit 5 (fir0_ena): 1; Bit 4 (fir1_ena): 1 (fir0, fir1 enabled (x4 interpolation))
CONFIG19 Bit 1 (multi_sync_sel): 1 (Single Sync Source mode with FRAME controlled signal from Xilinx FPGA implementation)
Test results: Not Sine wave output.
Q2: I have no ideas about why FIFO mode doesn't output the x4 interpolation Sine wave under this setting. Could you tell me what's wrong about this setting?
CONFIG0 Bit 6 (fifo_ena): 0 (FIFO mode disabled); Bit 5 (fifo_reset_ena): 1; Bit 4 (multi_sync_ena): 1 ; Bit [1:0] (mixer_func): 0x0
CONFIG1 Bit 5 (fir0_ena): 1; Bit 4 (fir1_ena): 1 (fir0, fir1 enabled (x4 interpolation))
CONFIG19 Bit 1 (multi_sync_sel): 1
Test results: Sine wave output with wrong interpolation (not x4, seems x2) test results.
Q3: Under Setting four, I find that the DAC output is with 16 levels per Sine wave cycle (I think that it's wrong because the sampling clock rate for 16-bit I-data is 16.384/2 (= 8.192 MHz) and
the digital Sine wave pattern is with frequency, 1.024 MHz and the samples per digital Sine wave pattern's cycle after interpolation should be 32 (32 = (8.192/1.024)x
4(interpolation)).
32 samples per digital Sine wave pattern's cycle after x4 (interpolation) is not the same as 16 levels per Analog Sine wave cycle and I think this is wrong (It seems x2
(interpolation) setting). ).
Could you tell me what's wrong about this setting?
Setting five: fir0 enabled, fir1 disabled (x2 interpolation) with FIFO mode disabled (Keeping the DACCLK as 16.384 MHz)
CONFIG0 Bit 6 (fifo_ena): 0 (FIFO mode disabled); Bit 5 (fifo_reset_ena): 1; Bit 4 (multi_sync_ena): 1 ; Bit [1:0] (mixer_func): 0x0
CONFIG1 Bit 5 (fir0_ena): 1; Bit 4 (fir1_ena): 0 (fir0 enabled, fir1 disabled (x2 interpolation))
CONFIG19 Bit 1 (multi_sync_sel): 1
Test results: No DAC output.
Q4: I have no ideas about why Bypass mode not work under this setting. Could you tell me what's wrong about this setting?
Setting six: fir0 disabled, fir1 enabled (x2 interpolation) with FIFO mode disabled (Keeping the DACCLK as 16.384 MHz)
CONFIG0 Bit 6 (fifo_ena): 0 (FIFO mode disabled); Bit 5 (fifo_reset_ena): 1; Bit 4 (multi_sync_ena): 1 ; Bit [1:0] (mixer_func): 0x0
CONFIG1 Bit 5 (fir0_ena): 0; Bit 4 (fir1_ena): 1 (fir0 disabled, fir1 enabled (x2 interpolation))
CONFIG19 Bit 1 (multi_sync_sel): 1
Test results: Not Sine wave output.
Q5: I have no ideas about why Bypass mode doesn't output the x2 interpolation Sine wave under this setting. Could you tell me what's wrong about this setting?
Best Regards,
Eric Tsai