Hi engineers:
I’ve got a question regarding the ADS131A04:
Is my following calculation correct:?
The maximum CLKIN is 25 MHz (7.3). Therefore the maximum ICLK(=SCLK) (see table 9.6.1.12) is 12.5MHz.
If crc and hamming code is deactivated. SCLK should be at least:
MIN_SCLK=5frames*24bit*85333kSPS=10,2MHz.
Therefore the maximum ADC data-rate per channel in synchronous master mode with 24bit is 85333kSPS.