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ADS1278: DRDY staying de-asserted for repeated periods of time

joti1
Prodigy 70 points
Part Number: ADS1278

I'm using the ADS-1278 to convert a number of channels in SPI mode (fixed).

I use the DRDY pin as an interrupt to the MCU and when DRDY triggers the data is read over the SPI bus in TDM mode.

The mode used is high-resolution and the clock input is ~5.2MHz so I am getting a DRDY interrupt at ~10KHz as expected.

My understanding is that the DRDY interrupt should continually trigger every time data is available.

However, I notice that there are repeated times where no DRDY occurs at the expected data rate frequency.

These delays last for approx. 500mS and then DRDY starts to get asserted again.

It looks like I keep getting a series of correct DRDY assertions followed by time periods where DRDY stays high - then it starts triggering again at the expected frequecy.

See the trace below - any ideas why this could be happening?

  • 0
    TI__Mastermind 39530 points

    Hello Joti1,

    After power-up, you should get a continuous /DRDY at the output data rate.  This seems like it could be some kind of noise issue, or a floating input pin.

    1.  Please verify that CLK is continuous (you stated 5.2MHz).

    2.  What is your SCLK frequency? In order to support 8 channels in fixed, TDM mode, it should either be set to 5.2MHz or 2.6MHz.

    3.  Verify that all input pins are pulled high or low as needed.  A change in any of these logic levels due to noise coupling will cause an internal reset, temporarily halting the /DRDY line.

    4.  Do you have AGND and DGND connected to the same ground plane directly next to the ADS1278?

    If you are comfortable sharing, please send a screenshot for the board layout around the ADS1278, along with schematics that show the input amp, reference, and power supply connections.

    Regards,
    Keith Nicholas
    Precision ADC Applications

  • 0 in reply to Keith Nicholas
    Prodigy 70 points

    Hi Keith,

    I'm using the ADS-1278 reference board connected via an SPI channel to a microcontroller board. 

    The SCK clock is continuous - to avoid any noise on the supplied clock I also tried replacing the 27MHz crystal with a 4MHz crystal on the reference board.

    This gave the same results - I got the required DRDY data rate of approx. 10Khz but see the DRDY pin staying high sometimes.

    It looks like I get a burst of DRDY pulses (for about 150mS), then the DRDY line stays high for ~580mS - this pattern keeps repeating.

     I was running the SCLK at a higher speed than SCK but I've brought it back down to the same speed now - however, this does not make any difference to the issue.

    Which input pins should be pulled high/low? - I'm using all 8 of the channels in TDM, fixed mode,

    thanks

  • 0 in reply to joti1
    TI__Mastermind 39530 points

    Hello Joti1,

    Are you pulsing the /SYNC pin after power-up?  We recommend this for proper operation, and this could be the cause of the erratic operation.

    Below are the fixed (high or low) pin configurations needed for high resolution mode, SPI, fixed TDM, 8 channels.

    1=IOVDD (High)
    0=GND (AGND=DGND=Low)

    1.  CLKDIV=1 (high resoulution)

    2.  DIN=0 (no daisy chain)

    3.  FORMAT0=1, FORMAT1=0, FORMAT2=0 (SPI, TDM, Fixed)

    4.  MODE0=1, MODE1=0 (high resolution)

    5. /PWDNx=1 (x=1..8, all channels enabled)

    6. TEST0=0, TEST1=0 (normal operation)

    In addition to the above signals, the following supply voltages should be provided to the board:

    1. AVDD=5V

    2. DVDD=1.8V

    3. IOVDD=3.3V (on-board oscillator specified for 3.3V only).

    SPI/MCU interface

    1. CLK continuous master clock.

    2. SCLK, spi serial clock, limited to ratios of SCLK/CLK 1, 1/2, 1/4, 1/8, etc.

    3. DOUT1, MISO data pin for SPI TDM mode.

    4. /DRDY, data ready output, continuous at output data rate

    5. /SYNC, pulse low for ADS1278 reset/synchronization, should be pulsed after power-up, and then remain high (IOVDD)

    Regards,
    Keith