This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

ADS1118: Value of conversion error parameter for specific condition

Part Number: ADS1118

Hi Team

My customer is using ADS1118 and he wants to know the value of conversion error parameter for specific condition since the value in datasheet is measured by

different condition. 

Is it possible to get the data for gain error, offset error and INL? for example, by simulation. Thanks.

Gain error

Offset error

INL

Condition

・Ambient temp:25℃

・power voltage:5.25V

・input signal:DC signal from OP amp

・Input serial resistor:3600Ω

・FSR:6.144V

・DR:250SPS

・input mode:single-end

Besides, the customer also wants to know if we have data showing relationship between input serial resistor and AD conversion error. 

And if there is no data for parameter that the customer is asking above, could you tell me if we can get it by calculation.  

Please let me know if you need more information. 

Thanks.

  • Hung Ching,


    I don't have any extra data to share, but there is plenty of information in the datasheet. Much of this is in the form of typical characteristics curves in the datasheet starting on page 10.

    For the gain error, I would look at Figure 17 in the datasheet. The gain error doesn't appear to change much between the different FSR settings and the overall drift is small.

    Also, I don't have much detail into the gain error vs supply, but Figure 18 seems to show that there isn't much variation in the gain error from the supply going from 2V to 5.5V in two other settings.

    I don't have any specific curves on offset with the FSR setting of ±6.144V, but the in general, I think the offset is similar in voltage through the gain setting. I would note that Figure 12 does seem to show an increase in offset voltage with supply. This is with a single-ended measurement.

    The INL should be very small. The datasheet lists one LSB, but you can see that with different supply voltages and different PGA settings, the INL will be much less than 1LSB.

    Again, these are typical curves. If you think of these as typical values, you can consider the error seen in these curves as the equivalent of a standard deviation of the error for each of these parameters.

    As for the series resistance, If the customer is using a filter capacitance with this series resistor, I would set the bandwidth to be about 10x of the data rate (in the customer's case about 2500Hz).

    I think that the contribution of the series resistance to the measurement error is small. It comes from the equivalent input impedance from the ADC. With the FSR set to ±6.144V, the equivalent input impedances can be taken from the electrical characteristics shown here:

    And the equivalent input impedance looks like this:

    With a single-ended measurement, the equivalent input is close to 8MΩ || 22MΩ. With 3.6kΩ series resistance at the input, I would expect less than 0.1% error. However, I wouldn't increase this series resistance. I generally like to keep this series resistance under 5kΩ, because the input sampling still needs to settle it's value during 1/2 of the modulator period. For this device, it is every 2us.


    Joseph Wu

  • Hi Joseph

    Thanks for the detailed explanation!

    I really appreciate it.

    I have two questions about what you mentioned.

    1. Again, these are typical curves. If you think of these as typical values, you can consider the error seen in these curves as the equivalent of a standard deviation of the error for each of these parameters.

    >Do you mean that the customer can infer the data that he wants from the provided curves in the datasheet? 

    2. I generally like to keep this series resistance under 5kΩ, because the input sampling still needs to settle it's value during 1/2 of the modulator period. For this device, it is every 2us.

    >I couldn't find the description "because the input sampling still needs to settle it's value during 1/2 of the modulator period." in the datasheet. If this is common sense could you kindly provide material which explains this for me, if there is any ? 

    Thanks.

  • Hung Ching,


    The typical curves shown give an approximate behavior of what a typical device may show. In general, you might try to infer some idea of how the device may behave with a larger sample size and some distribution. I don't have any other specific data to share so this is the only recommendation I have to give approximate behavior for this particular configuration.

    For the sampling, I mentioned half of the modulator period to settle because during each modulator period there is a sample and then a discharge. Along with Figure 36 that I showed in the previous post, there is Figure 37 which shows S1 and S2.

    The modulator period is tSAMPLE, and the inputs are sampled when S1 is high, which is about half of tSAMPLE.


    Joseph Wu