Part Number: ADC12DJ5200RF
Other Parts Discussed in Thread: TIDA-010128
Hi team,
With reference to the design below, the customer has designed the acquisition system of ADC12DJ5200RF+ FPGA + HMC07044 + LMK2595.
TIDA-010128 :Scalable 20.8 GSPS reference design for 12 bit digitizers
The ADC works in JMODE = 1 single channel,16 lanes,jesd204b compatible mode. LMK2595 outputs a 2.5GHz frequency clock and a single pulse form of sysref. HMC7044 sends REFCLK and sysref to FPGA, and ensures homology with LMK2595 input clock.
The initial phenomenon is that after sending sysref to ADC and FPGA, sync can be pulled up in test mode (ramp), but it will be pulled down occasionally. If it is set to normal mode, sync will be pulled down periodically. It seems that there is a problem with the sysref for ADC.
Now, the customer directly grounded the sysref pin of the ADC and only sent sysref to the FPGA. Actually, the link can be established. Sync can continue to be pulled up, not pulled down.
Customer wound like to know why? Does ADC not need sysref to synchronize LMFC when it works?