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Hi team,
With reference to the design below, the customer has designed the acquisition system of ADC12DJ5200RF+ FPGA + HMC07044 + LMK2595.
TIDA-010128 ：Scalable 20.8 GSPS reference design for 12 bit digitizers
The ADC works in JMODE = 1 single channel，16 lanes，jesd204b compatible mode. LMK2595 outputs a 2.5GHz frequency clock and a single pulse form of sysref. HMC7044 sends REFCLK and sysref to FPGA, and ensures homology with LMK2595 input clock.
The initial phenomenon is that after sending sysref to ADC and FPGA, sync can be pulled up in test mode (ramp), but it will be pulled down occasionally. If it is set to normal mode, sync will be pulled down periodically. It seems that there is a problem with the sysref for ADC.
Now, the customer directly grounded the sysref pin of the ADC and only sent sysref to the FPGA. Actually, the link can be established. Sync can continue to be pulled up, not pulled down.
Customer wound like to know why? Does ADC not need sysref to synchronize LMFC when it works?
Hi dear,Rob
The original figure is the following one which I referenced "TIDA-010128 ：Scalable 20.8 GSPS reference design for 12 bit digitizers". But when I sent sysref pulse to ADC and FPGA,the sync signal would be pulled down occasionally.
And then I change my schematic to the following one that the sysref pin of ADC12DJ5200 is grounded directly by DC coupling:
so I post my question:
"But I directly grounded the sysref pin of the ADC and sent sysref only to the FPGA.Then the link was established. It showed that Sync was solely pulled up without being pulled down.
But the manual says only when the pulse is sent to both ADC and FPGA and the LMFC is reset will the Sync takes on such status. How to explain this irregularity?
Or the truth is the link can also be established with sysref pin grounded and the LMFC not reset by sysref pulse?"
Look forward to your reply.
Regards,
Ty
Hi Ty,
See my comments and questions below....
Answer for Question1:The sample rate frequency is 10GSPS,in JMODE1,using DDR sample clock method.
Answer for Question2:And the frequency of sysref is 3.90625MHz.(R*fs/10/F/K/n)
then I recognize that the sysref signal is use for multi-device with Deterministic Latency.
and I am confused that if I want to synchronize multi-device with timestamp method, the manual says when N' equals to 12bit, the LSB of the 12bit represents the timestamp bit. The question is that how I recognize which meaning of the LSB, timestamp bit or sample data LSB bit?
RR: bit0 replaces the time stamp, see below in the datasheet...
Regards,
Rob
