Part Number: ADS114S06B
I am using ADS114S06B in one of our project. I am not getting proper data from the registers including device id. My program sequence is as follows :
SPI Settings : Baud Rate - 20Mbits/s,8 Bit data format, MSB first, CPOL-0, CPHA-1
Program flow :
1) Reset pin set to 0
2) Delay 10ms
3) Reset pin set to 1
4) Delay 100ms
5) CS pin set to 0
6) Send Reset command to spi (0x06)
7) CS pin set to 1
8) Delay 100ms
Read Chip ID
9) CS pin set to 0
10) Read Chip ID from ID register(0x00)
11) CS pin set to 1
Here i am getting 0x06 instead of 0x05 as mentioned in datasheet. Also other registers value is not matching with default value mentioned in the datasheet. If write some other value in registers and read back again, values are not same.
Kindly support me what wrong i am doing to short out the issue.
You need to make sure that you are following the timing requirements as shown in section 7.6 of the ADS114S06B datasheet. The minimum SCLK period is specified as 100ns which translates to a maximum SCLK frequency of 10MHz.
Also, some of the commands are multi-byte. The CS must remain low throughout the entire communication transaction for the commands sent. There is also timing specific to CS going low to the first rising edge of SCLK and the the last falling edge of SCLK and the rising edge of CS.
Slowing SCLK down and making sure CS stays low throughout the entire communication should improve your results. If you are still seeing issues, send me some scope or logic analyzer shots of the communication.
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In reply to Bob Benjamin:
Thanks for your quick reply. I will try again with your suggestions and update here.
In reply to Asish Banerjee:
I am sorry for my late reply as i was out of office for a couple of days. My problem solved after making CPOL = High, CPHA = 1 Edge and Baud Rete = 2.5Mhz in SPI port settings.
Thanks you again for your support.
Just for clarity the SCLK polarity should dwell low, which in most processors would be CPOL being low. As far as the phase, the usual condition is for CPHA to be high, where the rising edge of the SCLK the data changes and remains steady on the falling edge. Different processors may use different settings as to how the clock polarity and phase respond. So the best method for checking is to look at the signals on an oscilloscope or logic analyzer for verification at the ADS114S06B SPI interface pins. The signals should look similar to those shown in the timing diagrams in the datasheet.
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