ADS124S08: Absolute Input Current vs Differential Input Current - Part 2

Hi Darren,

I realize that these input currents are very confusing to decipher.  By adding the graphs it was our intent to show the characteristic behavior of the inputs and not necessarily to determine the total error.  Depending on the mode of operation (PGA enable and PGA disabled/bypassed) determines the actual outcome.  For example, if you enable the PGA and apply gain but exceed the input measurement range, your measurement is invalid regardless of what the graphs show.  Another way to put this is if my measurement is limited in range, then I would not look at the entire graph end to end with respect to absolute input current.  So when evaluating the graphs also keep in mind the notes in the electrical characteristics table regarding the conditions used for specifying min/max and typical behavior.

Here is an example of why the graphs are shown.  One of the concepts shown in the absolute input graphs is what happens with an unused input if I tie it to a specific voltage.  Often times a customer will have extra inputs that go unused and they want to tie the input to a specific voltage.  We suggest to leave it open, tie it high, tie it mid-analog supply or tie it low in that order.  The absolute input current graphs demonstrate why.

I will comment on your specific questions below.

Best regards,

Bob B

Darren (FAE) said:

Hi Bob,

I appreciate the quick reply to the above - my customer is still requesting some info on the mechanism though, so let me see if this understanding is correct⇓

1. Bob: Absolute Current graphs deal primarily with "leakage" from ESD structures, MUX, etc.

From Figure 10 in the DS, it looks like if AINx approaches 3.3V, the leakage goes "positive". I assume "positive" leakage current means current flows into the pin. I also assume this is because as AINx gets close to VCC + 0.3V (forward voltage drop of the ESD structure), current begins to flow through AINx to VCC, as the ESD structure is becoming forward biased, and this starts to dominate at high AINx voltage. [Bob] This is correct and the leakage is also dependent on temperature where internal circuitry also becomes more leaky.

From Figure 10 in the DS, it looks like when AINx is at the standard 1~2V range, the leakage current is "negative", which I assume means current is flowing out of the pin. I also assume this is because the internal circuitry (MUX, etc) is at some bias level higher than the 1~2V at AINx, which pushes some small current out of the pin. [Bob] Yes, a small current can flow due to the internal circuitry, but this is also temperature dependent as to the effect.

What confuses me, is that as the voltage at AINx continues to drop, and gets closer to 0V, the leakage current goes "positive" again at 25℃. I don't see how current could flow into the pin with such a low AINx voltage...why is this? [Bob] Note that Figure 10 is with PGA enabled at a gain of 1.  Also note that the input range is only viable AVSS + 0.15V to AVDD - 0.15V and outside of that range the PGA is operating in a non-linear region.  It is difficult to say what it actually happening in the non-linear region.  If the PGA is bypassed, then yes the extremes are more important such as in a single-ended measurement case.  Here is where it is important to note what it says in the electrical characteristics table for PGA bypassed where the typical current is specified within the input voltage range of AVSS + 0.1V and AVDD - 0.1V.

From the above:
- When current flows into the AINx pin, it draws some away from what the IDAC is sourcing.
- When current flows out of the AINx pin, it adds some into the path of the IDAC, "increasing" IDAC current [Bob] Here it becomes important to interpret the graphs correctly.  If you are making an RTD measurement, low-side reference, the design should place the input voltage of the RTD to about mid-analog supply.  It will never be at the input voltage extremes.  From the graph in Figure 10 at approximately 1.65V, the absolute current will be around the typical value of 100pA.

2. Bob: Differential Current graphs deal with input bias currents

The differential input current has a much wider scale for a given voltage difference. Let's say we had the following setup:

AIN1 = 2V
AIN2 = 1V

Here, the absolute input current for AIN1 and AIN2 should be within -25pA according to Figure 10, because of their absolute voltages. But Figure 12 shows that for a differential voltage of +1V, there is around a +500pA differential input current. 

From this, I assume that means AIN1 has 500pA more current flowing into the pin than AIN2 (positive current means current is leaking into the pin) So, how do you define which pin has what current flowing though it, based on Figure 10 and Figure 12? [Bob] Make sure that you are making and apples to apples comparison and not apples to oranges.  Figure 12 relates to PGA bypassed.  You should be using Figure 14.

Assuming a design safety margin of 1nA of differential input current, and exactly matched input resistors of 4kΩ, the AIN1 and AIN2 pins would "measure" a voltage difference of ~4uV, correct? And this is within the noise of the device? [Bob] The 1nA condition would be within the electrical characteristics table of +/- 1nA.  This would be based on the input voltage extremes of +/-2.5V.  If your input voltage is within say a few hundred mV, then you would be much closer to very little current flowing.  Look at the response between -0.2V and +0.2V and note that the typical differential current is quite small at around +/- 10pA.